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SL11R cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-08006 rev. ** revised december 3, 2001 SL11R usb controller/ 16-bit risc processor data sheet
SL11R document #: 38-08006 rev. ** page 2 of 85 table of contents 1.0 definitions .............................................................................................................. .................... 8 2.0 references ............................................................................................................... ................. 8 3.0 introduction ............................................................................................................. ................ 8 3.1 overview ................................................................................................................. ........................ 8 3.2 SL11R features ........................................................................................................... ................... 8 3.3 SL11R 16-bit risc processor .............................................................................................. ...... 10 3.4 3kx16 mask rom and bios .................................................................................................. ...... 10 3.5 internal ram ............................................................................................................. .................... 10 3.6 clock generator .......................................................................................................... ................. 11 3.7 usb interface ............................................................................................................ ................... 11 3.8 processor control registers .............................................................................................. ........ 11 3.9 interrupts ............................................................................................................... ....................... 11 3.10 uart interface .......................................................................................................... ................. 11 3.11 *2-wire serial eeprom interface ......................................................................................... ..... 11 3.12 external sram/dram/eprom interface ................................................................................. 11 3.13 general timers and watch dog timer ..................................................................................... 1 1 3.14 special gpio functionality for suspend, resume and low power modes ......................... 11 3.15 programmable pulse/pwm interface ....................................................................................... 1 1 3.16 mailbox and dma overview ................................................................................................ ...... 12 3.17 mailbox interface ....................................................................................................... ................ 12 3.18 dma interface ........................................................................................................... .................. 13 3.19 fast dma mode ........................................................................................................... ............... 14 3.20 SL11R interface modes ................................................................................................... .......... 14 3.20.1 general purpose io mode (gpio) ........................................................................................ ........... 15 3.20.2 8/16-bit dma mode ..................................................................................................... ...................... 15 3.20.3 fast epp mode ......................................................................................................... ......................... 15 3.20.4 dvc 8-bit dma mode .................................................................................................... ....................15 4.0 interface ................................................................................................................ .................. 15 4.1 internal masked rom: 0xe800-0xffff ...................................................................................... 1 5 4.2 external rom: 0xc100-0xe800 .............................................................................................. ..... 15 4.3 internal ram: 0x0000-0x0bff .............................................................................................. ...... 16 4.4 clock generator .......................................................................................................... ................. 16 4.5 usb interface ............................................................................................................ ................... 18 4.5.1 usb global control & status register (0xc080: r/w) ....................................................................1 8 4.5.2 usb frame number register (0xc082: read only) ........................................................................ 18 4.5.3 usb address register (0xc084: r/w) ..................................................................................... .........18 4.5.4 usb command done register (0xc086: write only) ...................................................................... 19 4.6 usb endpoint 0 control & status register (0xc090: r/w) ...................................................... 19 4.7 usb endpoint 1 control & status register (0xc092: r/w) ...................................................... 19 4.8 usb endpoint 2 control & status register (0xc094: r/w) ...................................................... 19 4.9 usb endpoint 3 control & status register (0xc096: r/w) ...................................................... 19 4.9.1 general description for all endpoints from endpoint 0 to endpoint 3 ......................................... 19 4.9.2 usb endpoints control (for writing) .................................................................................... ........... 19 4.9.3 usb endpoints status (for reading) ..................................................................................... .......... 20 4.9.4 usb endpoint 0 address register (0x0120: r/w) .......................................................................... .20 4.9.5 usb endpoint 1 address register (0x0124: r/w) .......................................................................... .20 4.9.6 usb endpoint 2 address register (0x0128: r/w) .......................................................................... .20 4.9.7 usb endpoint 3 address register (0x012c: r/w) .......................................................................... 20
SL11R document #: 38-08006 rev. ** page 3 of 85 table of contents (continued) 4.9.8 usb endpoint 0 count register (0x0122: r/w) ............................................................................ ...20 4.9.9 usb endpoint 1 count register (0x0126: r/w) ............................................................................ ...20 4.9.10 usb endpoint 2 count register (0x012a: r/w) ........................................................................... .20 4.9.11 usb endpoint 3 count register (0x012e: r/w) ........................................................................... .. 21 4.10 processor control registers ............................................................................................. ....... 21 4.10.1 configuration register (0xc006: r/w) .................................................................................. ......... 21 4.10.2 speed control register (0xc008: r/w) .................................................................................. ........ 22 4.10.3 power down control register (0xc00a: r/w) ............................................................................. .. 23 4.10.4 breakpoint register (0xc014: r/w) ..................................................................................... ........... 23 4.11 interrupts .............................................................................................................. ...................... 23 4.11.1 hardware interrupts ................................................................................................... ...................... 24 4.11.2 interrupt enable register (0xc00e: r/w) ............................................................................... ........24 4.11.3 gpio interrupt control register (0xc01c: r/w) ......................................................................... ...25 4.11.4 software interrupts ................................................................................................... ........................ 25 4.12 uart interface. ......................................................................................................... ................. 27 4.12.1 uart control register (0xc0e0: r/w) ................................................................................... ........ 27 4.12.2 uart status register (0xc0e2: read only) .............................................................................. .... 28 4.12.3 uart transmit data register (0xc0e4: write only) ..................................................................... 2 8 4.12.4 uart receive data register (0xc0e4: read only) ...................................................................... 28 4.13 serial eeprom interface (2-wire serial interface) .................................................................. 28 4.14 external sram, eprom, dram .............................................................................................. .29 4.14.1 memory control register (0xc03e: r/w) ................................................................................. ......30 4.14.2 extended memory control register (0xc03a: r/w) ...................................................................... 30 4.14.3 extended page 1 map register (0xc018: r/w) ............................................................................ .. 30 4.14.4 extended page 2 map register (0xc01a: r/w) ............................................................................ .31 4.14.5 dram control register (0xc038: r/w) ................................................................................... ....... 31 4.14.6 memory map ............................................................................................................ .......................... 31 4.15 general timers and watch dog timer ..................................................................................... 3 3 4.15.1 timer 0 count register (0xc010: r/w) .................................................................................. ......... 33 4.15.2 timer 1 count register (0xc012: r/w) .................................................................................. ......... 33 4.15.3 watchdog timer count & control register (0xc00c: r/w) ......................................................... 33 4.16 special gpio function for suspend, resume and low-power modes ................................ 33 4.17 programmable pulse/pwm interface ....................................................................................... 3 4 4.17.1 pwm control register (0xc0e6: r/w) .................................................................................... ........ 34 4.17.2 pwm maximum count register (0xc0e8: r/w) ............................................................................. 3 5 4.17.3 pwm channel 0 start register (0xc0ea: r/w) ............................................................................ .. 35 4.17.4 pwm channel 0 stop register (0xc0ec: r/w) ............................................................................. .36 4.17.5 pwm channel 1 start register (0xc0ee: r/w) ............................................................................ .. 36 4.17.6 pwm channel 1 stop register (0xc0f0: r/w) ............................................................................. .. 36 4.17.7 pwm channel 2 start register (0xc0f2: r/w) ............................................................................ ...36 4.17.8 pwm channel 2 stop register (0xc0f4: r/w) ............................................................................. .. 36 4.17.9 pwm channel 3 start register (0xc0f6: r/w) ............................................................................ ...36 4.17.10 pwm channel 3 stop register (0xc0f8: r/w) ............................................................................ .37 4.17.11 pwm cycle count register (0xc0fa: r/w) ............................................................................... ..37 4.18 fast dma mode ........................................................................................................... ............... 37 4.18.1 dma control register (0xc02a: r/w) .................................................................................... ........ 37 4.18.2 low dma start address register (0xc02c: r/w) ......................................................................... 3 7 4.18.3 high dma start address register (0xc02e: r/w) ......................................................................... 38 4.18.4 low dma stop address register (0xc030: r/w) ..........................................................................3 8 4.18.5 high dma stop address register (0xc032: r/w) ......................................................................... 3 8
SL11R document #: 38-08006 rev. ** page 4 of 85 table of contents (continued) 5.0 SL11R interface modes .................................................................................................... .... 38 5.1 general purpose io mode (gpio) ........................................................................................... ... 38 5.1.1 i/o control register 0 (0xc022: r/w) ................................................................................... ............ 39 5.1.2 i/o control register 1 (0xc028: r/w) ................................................................................... ............ 39 5.1.3 output data register 0 (0xc01e: r/w) ................................................................................... .......... 39 5.1.4 output data register 1 (0xc024: r/w) ................................................................................... .......... 39 5.1.5 input data register 0 (0xc020: read only) .............................................................................. ........ 39 5.1.6 input data register 1 (0xc026: read only) .............................................................................. ........ 39 5.2 8/16-bit dma mode ........................................................................................................ ............... 40 5.2.1 mailbox protocol ....................................................................................................... .......................... 41 5.2.2 inbuff data register (0xc0c4: r/w) ..................................................................................... .........41 5.2.3 outbuff data register (0xc0c4: r/w) .................................................................................... ...... 41 5.2.4 status register (0xc0c2: read only) .................................................................................... ....... 42 5.2.5 dma protocol ........................................................................................................... ........................... 42 5.2.6 dma control register (0xc0c0: r/w) ..................................................................................... .........42 5.3 fast epp mode ............................................................................................................ ................. 42 5.3.1 epp data register (0xc040: r/w) ........................................................................................ ............. 43 5.3.2 epp address register (0xc044: r/w) ..................................................................................... .........43 5.3.3 epp address buffer read register (0xc046: read only) .............................................................. 43 5.3.4 epp data buffer read register (0xc042: read only) ..................................................................... 4 3 5.3.5 epp status data register (0xc04e: r/w) ................................................................................. ........ 43 5.3.6 epp p_reg register (0xc050: r/w) ....................................................................................... .......... 44 5.3.7 serial interface registers ............................................................................................. ..................... 44 5.3.7.1 serial interface control & status register ........................................................................... .................... 44 5.3.7.2 serial interface address register ..................................................................................... ......................... 44 5.3.7.3 serial interface data write register.................................................................................. ......................... 44 5.3.7.4 serial interface data read register .................................................................................. ........................ 45 5.4 dvc 8-bit dma mode ....................................................................................................... ............ 45 5.4.1 video status register ................................................................................................... ...................... 45 5.4.2 camera serial interface registers ...................................................................................... ..............46 5.4.3 serial interface control & status register (0xc068: r/w) .............................................................. 4 6 5.4.4 serial interface address register (0xc06a: write only) ................................................................ 4 6 5.4.5 serial interface data write register (0xc06c: write only) ............................................................. 4 6 5.4.6 serial interface data read register (0xc06c: read only) ............................................................. 47 5.4.7 i/o address map ........................................................................................................ ......................... 47 6.0 physical connection ...................................................................................................... ..... 49 6.1 package type ............................................................................................................. .................. 49 6.2 gpio and 8/16-bit dma modes?pin assignment and description ........................................ 49 6.3 fast epp pin assignment and description ............................................................................... 52 6.4 dvc 8-bit dma mode pin assignment and description .......................................................... 54 7.0 SL11R cpu programming guide ......................................................................................... 57 7.1 instruction set overview ................................................................................................. ............ 57 7.2 reset vector ............................................................................................................. .................... 57 7.3 register set ............................................................................................................. ..................... 57 7.4 general-purpose registers ................................................................................................ ........ 57 7.5 general purpose/address registers ........................................................................................ .58 7.6 regbank register (0xc002: r/w) ........................................................................................... .58 7.7 flags register (0xc000: read only) ....................................................................................... ... 58 7.8 instruction format ....................................................................................................... ................ 58
SL11R document #: 38-08006 rev. ** page 5 of 85 table of contents (continued) 7.9 addressing modes ......................................................................................................... .............. 59 7.10 register addressing ..................................................................................................... ............. 59 7.11 immediate addressing .................................................................................................... .......... 59 7.12 direct addressing ....................................................................................................... ............... 59 7.13 indirect addressing ..................................................................................................... .............. 59 7.14 indirect addressing with auto increment ............................................................................... 60 7.15 indirect addressing with offset ......................................................................................... ...... 60 7.16 stack pointer (r15) special handling .................................................................................... .. 60 7.17 dual operand instructions ............................................................................................... ......... 60 7.18 program control instructions ............................................................................................ ....... 62 7.19 single operand operation instructions ................................................................................... 63 7.20 miscellaneous instructions .............................................................................................. ......... 65 7.21 built-in macros ......................................................................................................... .................. 65 7.22 SL11R processor instruction set summary ........................................................................... 66 8.0 SL11R - electrical specification ..................................................................................... 67 8.1 absolute maximum ratings ................................................................................................. ....... 67 8.2 recommended operating conditions ....................................................................................... 67 8.3 crystal requirements (xtal1, xtal2) ..................................................................................... 6 8 8.4 external clock input characteristics (xtal1) .......................................................................... 68 8.5 SL11R dc characteristics ................................................................................................. ......... 68 8.6 SL11R usb transceiver characteristics ................................................................................... 6 9 8.7 SL11R reset timing ....................................................................................................... ............. 69 8.8 SL11R clock timing specifications ........................................................................................ ... 69 8.9 8/16-bit dma & dvc 8-bit dma mode: sdata port i/o read cycle (non-dma) .................... 70 8.10 8/16-bit dma & dvc 8-bit dma mode: sdata port i/o write cycle (non-dma) .................. 71 8.11 8/16-bit dma & dvc 8-bit dma mode: sdata, dma read cycle ........................................ 72 8.12 8/16-bit dma & dvc 8-bit dma mode: sdata, dma write cycle ......................................... 72 8.13 SL11R signals name convention ........................................................................................... .. 72 8.14 SL11R dram timing ....................................................................................................... .......... 73 8.15 SL11R dram read cycle .................................................................................................. ...... 74 8.16 SL11R dram write cycle ................................................................................................. ....... 75 8.17 SL11R cas-before-ras refresh cycle ................................................................................... 76 8.18 SL11R dram page mode read cycle ..................................................................................... 77 8.19 dram page mode write cycle .............................................................................................. ... 78 8.20 SL11R sram read cycle ................................................................................................... ....... 79 8.21 SL11R sram write cycle .................................................................................................. ....... 80 8.22 2-wire serial interface eeprom timing .................................................................................. 8 1 8.23 fast epp data/address read cycle ........................................................................................ .82 8.24 fast epp data/address write cycle ....................................................................................... .82 9.0 package information ...................................................................................................... .... 83 9.1 drawings and dimensions .................................................................................................. ........ 83 9.2 package markings ......................................................................................................... .............. 84 9.3 thermal specifications ................................................................................................... ............ 84 10.0 revision history ........................................................................................................ ........... 85
SL11R document #: 38-08006 rev. ** page 6 of 85 list of figures figure 3-1. SL11R block diagram .............................................................................................. ...... 10 figure 3-2. functional logic diagram .......................................................................................... .... 12 figure 3-3. mailbox/dma read ................................................................................................. ........ 13 figure 3-4. mailbox/dma write ................................................................................................ ......... 14 figure 4-1. 48-mhz crystal circuit ........................................................................................... ........ 17 figure 4-2. 12-mhz crystal circuit ........................................................................................... ........ 17 figure 4-3. uart port connection ............................................................................................. ...... 27 figure 4-4. 2-wire serial interface 2k-byte connection ................................................................. 29 figure 4-5. 2-wire serial interface 16k connection ....................................................................... 29 figure 4-6. special gpio pull-up connection example ................................................................. 34 figure 4-7. pwm block diagram ................................................................................................ ....... 34 figure 5-1. gpio mode block diagram\ ......................................................................................... .. 40 figure 5-2. 8/16-bit dma mode block diagram ............................................................................... 41 list of tables table 4-1. internal masked rom (SL11R bios) .............................................................................. 15 table 4-2. internal ram memory usage ......................................................................................... .16 table 4-3. hardware interrupt table .......................................................................................... ....... 24 table 4-4. software interrupt table .......................................................................................... ........ 26 table 4-5. memory map ........................................................................................................ ............. 32
SL11R document #: 38-08006 rev. ** page 7 of 85 license agreement use of this document and the intellectual properties contained herein indicates acceptance of the following license agreement. if you do not accept the terms of this license agreement, do not use this document, nor the associated intellectual properties, nor any other material you received in association with this product, and return this document and the associated materials wit hin fifteen (15) days to cypress semiconductor corporation or (cy) or cy ? s authorized distributor from whom you purchased the product. 1. you can only legally obtain cy ? s intellectual properties contained in this document through cy or its authorized distributors. 2. you are granted a nontransferable license to use and to incorporate cy ? s intellectual properties contained in this document into your product. the product may be either for your own use or for sale. 3. you may not reverse-engineer the SL11R or otherwise attempt to discover the designs of SL11R. 4. you may not assign, distribute, sell, transfer, or disclose cy ? s intellectual properties contained in this document to any other person or entity. 5. this license terminates if you fail to comply with any of the provisions of this agreement. you agree upon termination to des troy this document, stop using the intellectual properties contained in this document and any of its modification and incorporated or merged portions in any form, and destroy any unused SL11R chips. warranty disclaimer and limited liability cypress semiconductor corporation makes no warranty for the use of its products, other than those expressly contained in the company ? s standard warranty which is detailed in cypress ? s terms and conditions located on the company ? s web site. the company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. no licenses to patents or other intellectual property of cypress are granted by the company in connection with the sale of cypress products, expressly or by implication. cypress ? s products are not authorized for use as critical components in life support devices or systems. SL11R is a trademark of the cypress semiconductor corporation. all other product names are trademarks or registered trade- marks of their respective owners.
SL11R document #: 38-08006 rev. ** page 8 of 85 1.0 definitions usb u niversal s erial b us SL11R the SL11R is a cypress usb controller, which provides multiple functions on a single chip. qt q uick stream data t ransfer engine, which contains a small set of risc instructions designed for the SL11R usb controller. qts ? qt ? is a naming convention that represents qt engine utility tools. for example: ? qts ? indicates all tools, which interface with the rs232 serial interface port. qtu qt engine tools that interface with the usb port r/w read/write pll p hase l ock l oop. pwm p ulse w idth m odulation dvc d igital v ideo c amera mfu m ulti f unction u nits wdt w atch d og t imer ram r andom a ccess m emory epp e nhanced p arallel p ort: an asynchronous, byte-wide, bidirectional channel controlled by the host de- vice. this mode provides separate address and data cycles over the eight data lines of the interface. 2-wire serial interface 2-wire serial eeprom interface. r0-r15 SL11R registers: r0-r7 data registers or general-purpose registers. r8-r14 address/data registers, or general-purpose registers. r15 stack pointer register. SL11R bios a simulation model similar to 80x86 bios 2.0 references [ref. 1] SL11R_bios [ref. 2] SL11R_tools [ref. 3] universal serial bus specification 1.1 3.0 introduction 3.1 overview the SL11R is a low-cost, high-speed universal serial bus (usb) risc based controller. it contains a 16-bit risc processor with built-in SL11R bios rom to greatly reduce firmware development work. its 2-wire serial eeprom interface offers low cost storage for usb device configuration and customer ? s product-specific functions. new functions can be programmed into the 2-wire serial interface by downloading them from a usb host pc. this unique architecture provides the ability to upgrade products in the field without changing the peripheral hardware. the SL11R processor can execute code from either internal rom/ram or external rom and sram. the SL11R programmable bidirectional data port supports both dma and i/o modes. a built in usb port supports data transfers up to 12 mbits/sec which is the maximum usb transfer rate. all usb protocol modes are supported: isochronous (up to 1024 bytes/packet), bulk, interrupt, and control. the SL11R requires a 3.3-volt power supply, which can be powered via a usb host pc or a hub. suspend/resume, and low power modes are available. the SL11R offers an optimal solution for a variety of peripheral products such as: scanners, digital cameras (video and still), color printers, multi-function units (mfu), faxes, external storage devices, monitors, connectivity boxes, and other peripheral s that traditionally interface via epp or scsi to a host pc. 3.2 SL11R features cypress offers a development kit for each of its product lines. these development kits include multiple peripheral mini-port class drivers for windows 98/me/2000, firmware source code and demo usb source code for a variety of applications. also available is an SL11R ? c ? compiler, debugger, and assembler with a reference demo board. 48 mhz 16 bit risc processor up to 16 bits of programmable bidirectional data i/o
SL11R document #: 38-08006 rev. ** page 9 of 85 up to 32 bits of general purpose i/o (gpio) 6kx8 internal mask rom with built-in bios in supporting a comprehensive list of interrupt calls (see [ref. 1] SL11R_bios for detailed information). these include usb functions, 2-wire serial interface, and uart and boot-up options (boot-up from 2-wire serial interface or external rom). executable code can also run from 8-bit or 16-bit external memory. 3kx8 internal ram that can be configured as the usb ping-pong buffer for usb data0 and data1 packets. it also can be used for data and/or code. two-wire serial eeprom interface port with SL11R bios support to allow on-board eeprom programming flexible programmable external memory wait-states and a 8/16 data path up to 16-bit address for extended memory interface port for external sram and rom on chip dram controller on chip fast epp interface on chip 8/16-bit dma data path interface supports 12 mhz/48mhz external crystal or clock executable code or data can be loaded either from the usb port or via the uart port. the code/data is moved to ram for debugging purposes (using a break point register), or to be programmed via a two-wire serial eeprom. usb port (12 mbits/sec), including a built-in usb transceiver. all usb standard protocol modes are supported: isochronous mode (up to 1024 packet size), bulk, interrupt, and control modes. there are four available endpoints. each endpoint utilizes a bidirectional dma port to move data between the memory and the usb. data can be sent/received to/from the data port independently. two general purpose timers, a watchdog timer (wdt), four programmable pwm channels, and four programmable timing generator outputs four pwm or programmable timing generator output channels are available. each channel provides a programmable timing generator sequence that can be used to interface to various ccd, cis, and cmos image sensors, or can be used for other types of applications. suspend/resume and low power modes are supported uart interface supports from 900 baud to 115.2k baud usb generic mini-port driver for win98/2000 is available debugger and qt-assembler are available ? c ? compiler option available package: 100 lpqfp power requirements 3.3v
SL11R document #: 38-08006 rev. ** page 10 of 85 figure 3-1. SL11R block diagram 3.3 SL11R 16-bit risc processor the SL11R can be used as a general purpose 16 bit embedded processor. it includes a usb interface (universal serial bus) and up to 32 bits of gpio supporting a variety of functions and modes. the 16-bit main data port can be used in either i/o or dma bidirectional modes. also, the SL11R contains 4 pwm channels or four programmable time generator (ptg) signals, a uart, a 2-wire serial eeprom interface, an additional external dram or sram interface for extended memory, two timers, a watchdog timer, an internal mask bios rom (3kx16) and an sram (3kx8). the SL11R is optimized to offer maximum flexibility in the implementation of a variety of applications such as: embedded digital video usb controller, usb scanner controller, usb cable modems, printers, external storage devices, mfu, etc. the SL11R contains a specialized instruction set (risc) that is highly optimized to provide efficient coding for a variety of applications such as video processing algorithms, network data packet translation and usb transaction processing. the SL11R includes a simple software interface for all usb transaction processing, which supports bulk mode (up to 64 bytes/packet), isochronous mode (up to 1024 bytes/packet), all interrupt and control modes. 3.4 3kx16 mask rom and bios the SL11R has a built in 3kx16 mask rom that contains the SL11R bios. this bios rom provides the software interface for the usb and a boot-up option for a 2-wire serial interface or an external 8/16 eeprom. 3.5 internal ram the SL11R contains 3k x 8 internal ram. the ram can be used for code/program, variables, buffer i/o, dma data (i.e. video data), and usb packets. this memory can be accessed by the 16-bit processor for data manipulation or by the sie (serial interface engine), which receives or sends usb host data. 6huldo ,qwhuidfh (qjlqh 6,( 86%,qwhuidfh 7udqvfhlyhu 'dwd 'dwd 8$57 ru *3,2 7[g 5[g 'dwd3ruw 3urjudppde oh %l'luhfwlrqdo '0$ru,2 16

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SL11R document #: 38-08006 rev. ** page 11 of 85 3.6 clock generator a 12, 48 mhz external crystal, or logic-level clock can be used with the SL11R. two pins, x1 and x2, are provided to connect a low cost crystal circuit to the device. if a logic-level clock is available, it may be connected directly to the x1 pin instead of a crystal. register c006 must be configured appropriately depending on the frequency used. 3.7 usb interface the SL11R has a built-in sie and usb transceiver that meet the usb (universal serial bus) specification v1.1. the transceiver is capable of transmitting or receiving serial data at the usb maximum data rate of 12 mbits/sec. the SL11R controller supports four endpoints. endpoint 0 is the default pipe and is used to initialize and manipulate the peripheral device. it also provides access to the peripheral device ? s configuration information, and supports control transfers. endpoint 1,2, and 3 support interrupt transfers, bulk transfers (up to 64 bytes/packet), or isochronous transfers (up to 1024 bytes/packet size). 3.8 processor control registers the SL11R provides software control registers that can be used to configure the chip mode, the clock generator, the software breakpoint, and to read the bios version. 3.9 interrupts the SL11R provides 127 interrupt vectors for it ? s bios software interface (see [ref. 1] SL11R_bios). 3.10 uart interface the SL11R has a built-in uart interface, which supports data rates from 900 baud to 115.2k baud. it can be used as a development port or for other interface requirements. the cypress development environment for the SL11R chip includes a debugger and assembler. optional ? c ? compiler is also available [1] . you can download modified code to internal sram and debug it using the built-in breakpoint register and breakpoint interrupt to break on any specified address location. 3.11 * 2-wire serial eeprom interface the SL11R provides an interface to an external serial eeprom. the interface is implemented using general purpose i/o signals. a variety of serial eeprom formats can be supported; currently the bios rom supports a two-wire serial eeprom. a serial eeprom can be used to store specific peripheral usb configuration and value-added functions. in addition, serial eeprom can be used for field product upgrades. 3.12 external sram/dram/eprom interface the SL11R provides a multiplexed address port and an 8/16-bit data port. this port can be configured to interface to an externa l sram, eprom or dram. the port provides nras; ncasl, ncash, ndramwr and ndramoe control signals for data access and refresh cycles to the dram. 3.13 general timers and watch dog timer the SL11R has two built in programmable timers that can provide an interrupt to the SL11R engine. on every clock tick which is 1 microsecond the timers decrement. an interrupt occurs when the timer reaches zero. a separate watchdog timer is also provided to provide a fail-safe mechanism. the watchdog timer can also interrupt the SL11R processor. 3.14 special gpio functionality for suspend, resume and low power modes the SL11R cpu supports suspend, resume and cpu low power modes. the SL11R bios assigns gpio29 for the usb data+ line pull-up (this pin can simulate usb cable removal or insertion while the usb power is still applied to the board) and the g pio20 for controlling the power off function. 3.15 programmable pulse/pwm interface the SL11R has four built-in pwm output channels available under 8/16-bit dma mode. each channel provides a programmable timing generator sequence that can be used to interface to various lines ccd, cis, cmos image sensors or can be used for other various applications. this feature is only available in the 8/16-bit dma mode. note: 1. contact cypress for details. (support@scanlogic.com)
SL11R document #: 38-08006 rev. ** page 12 of 85 3.16 mailbox and dma overview the mailbox and dma protocol use the same data latching and steering logic, so it is important to note that in a system where both mechanisms are used, the system designer must be careful to ensure that one type of transfer is finished before the next i s started. setting bits 1 and 2 to ? 1 ? in register 0xc006 enables the mailbox/dma interface. all transfers to and from the data registers are made through gpio 0 to 15. data written into the SL11R is latched into a 16-bit register on the rising edge of nw r (gpio 17) when addr (gpio 19) is high and ncs (gpio 18) is low. data is read out of the SL11R by asserting nrd (gpio 16) low while addr (gpio 19) is high and ncs (gpio 18) is low. this also applies when data is written or read during dma transfers. a functional logic diagram is shown in figure 3-2 . figure 3-2. functional logic diagram 3.17 mailbox interface the mailbox interface is accessed through three registers: 1. inbuff data register (0xc0c4; SL11R read) 2. outbuff data register (0xc0c4; SL11R write) 3. status register (0xc0c2: read only) when data is transferred to the SL11R through the mailbox interface, the external system must perform the transfer based on the values in the status register. when a word is written to the SL11R, the ? if ? (inbuff full) bit in the status register (0xc0c2) is set by the SL11R hardware. this bit must be polled until it is cleared to ? 0 ? by the SL11R. this indicates that the word has been accepted by the SL11R and that it is ready for another word. when data is read from the SL11R, the ? of ? (outbuff full) bit in the status register will be set by the SL11R when valid data is available. when the data is read by the external system, thi s bit will be cleared by the SL11R hardware. when a new word is available, the of bit will again be set.\ nwr/gpio17 sd15-0 ncs/gpio18 addr/gpio19 dq internal data bus inbuff_full (reg 0xc0c2 bit1) reset clr_inbuff_full ncs/gpio18 addr/gpio19 nrd/gpio16 internal data bus sd15-0 (1 of 16) (1 of 16) dq fig.1 - input data latch fig.2 - output data enable
SL11R document #: 38-08006 rev. ** page 13 of 85 3.18 dma interface this interface uses the same hardware as the mailbox interface, except that the dma engine inside the SL11R generates dma requests to control the transfer. because the dma engine handles the transfer of data through the input and output buffer, ther e is no need for the external system to poll the status register. the external system simply waits for a dreq (gpio 20) from the SL11R and transfers data. the SL11R dma engine can transfer data in only one direction at a time. please note that only 16-bit dma transfers are supported on the SL11R. the 22-bit dma counter is loaded through registers 0xc02c and 0xc02e. this makes up the dma start address and the location of the first word to be written or read. the 22-bit dma end address register is loaded through registers 0xc030 and 0xc032. thi s will be location of the last word written into the SL11R. when reading data out of the SL11R, the end address register should b e loaded with the last address to be read from plus two . after these registers are loaded, the dma control register (0xc0c0) must be loaded with a 0x0007 to enable the dreq output pin. lastly, the other dma control register (0xc02a) is loaded with either a 0x0001, to start dma transfers into the SL11R, or 0x0003, to start dma transfers out of the SL11R. figure 3-3. mailbox/dma read parameter description min. typical max. unit t cdq pclk to dreq high 1 17 ns t apw addr pulse width 30 ns t cpw ncs pulse width 30 ns t rpw read pulse width 30 ns t rah addr hold after read high 0 ns t rch ncs hold after read high 0 ns t acc read access time 25 ns t dcs dreq high to cs low 5 ns t dr dreq high to read low 5 ns t rhdq read high to dreq low hold 30 ns t rdh read high to data hold 10 ns nrd/gpio16 sd15-0 dreq/gpio20 ncs/gpio18 addr/gpio19 pclk t cdq t dcs t cpw t rpw t acc t rdh data valid t rhdq t apw t dr t rch t rah
SL11R document #: 38-08006 rev. ** page 14 of 85 figure 3-4. mailbox/dma write 3.19 fast dma mode this mode is currently used by the dvc 8-bit dma and 8/16-bit dma modes. in the dvc 8-bit dma mode, the dma data path will be 8-bits, which correspond to sd0-sd7. in the 8/16-bit dma mode, the dma data path can be configured to either 8 or 16 bi ts. 3.20 SL11R interface modes the SL11R has four modes. they are: general purpose i/o mode, fast epp mode, 8-bit dma mode, and 8/16-bit dma mailbox protocol ports mode. these modes are shared and can be configured under software control. note : the uart and 2-wire serial interface i/o pins are fixed in all cases. parameter description min. typical max. unit t cdq pclk to dreq high 1 17 ns t apw addr pulse width 20 ns t cpw ncs pulse width 20 ns t cws ncs low to write high setup 10 ns t wrpw write pulse width 10 ns t wah addr hold after read high 5 ns t wch ncs hold after read high 5 ns t dws data setup to write high setup 10 ns t dcs dreq high to cs low 5 ns t whdq write high to dreq low hold 30 ns t dw dreq high to write low 5 ns t wdh write high to data hold 5 ns nwr/gpio17 sd15-0 dreq/gpio20 ncs/gpio18 addr/gpio19 pclk t cdq t dcs t cpw t wrpw t dws t wdh data valid t whdq t dw t apw t wch t wah t cws
SL11R document #: 38-08006 rev. ** page 15 of 85 3.20.1 general purpose io mode (gpio) in the gpio mode, the SL11R has up to 32 general-purpose io signals available. however, four pins that are used by the uart and the 2-wire serial interface that cannot be used as gpio pins. a typical application for this gpio is the parallel port to u sb. the SL11R executes at 48mhz, which is fast enough to generate any parallel port timing. the SL11R also includes a special mode for epp timing designed for special devices that have no delay in epp mode. on any other available general purpose programmable i/o, the pins can be programmed for peripheral control and/or status. note : the fast dma and pwm interfaces are not supported in this mode. 3.20.2 8/16-bit dma mode this mode includes the mailbox protocol and dma protocol. the mailbox protocol allows asynchronous exchange of data between the external processor (i.e. dsp or other microprocessor) and SL11R via sd0-sd15 (gpio 0-15) which is a bidirectional data port. the dma protocol allows large blocks of data to be transferred to or from the SL11R via the 8/16-bit dma port. 3.20.3 fast epp mode this mode is designed to interface with a special optimized high-speed epp interface. in this mode, the SL11R processor has direct access to the epp control port. note : the fast dma and pwm interface are not supported in this mode. 3.20.4 dvc 8-bit dma mode this dvc 8-bit dma mode is designed to interface with ccd cameras. camera control and setup is performed through the serial control bus. the SL11R 16-bit processor has direct access to the control port and the camera operation is dependent on com- mands passed from the usb host to the SL11R. raw video data from the ccd camera is input to the SL11R on the 8-bit video data bus (sd7-sd0) using a combination of clock, control signals and 8-bit dma. note : the pwm interface is not supported in this mode. 4.0 interface 4.1 internal masked rom: 0xe800-0xffff the SL11R has a built-in 3kx16 internal masked rom that contains software bootstrap code to allow programs in an external 8/16-bit rom to be executed. the rom code can also load data from the 2-wire serial interface into internal ram for execution. in addition, the internal bios rom contains the interrupt service routines (see [ref. 1] SL11R_bios for information) that support the usb, 2-wire serial interface, uart interfaces and boot-up options (boot-up from 2-wire serial interface or external rom). this SL11R bios rom eases software development of all SL11R interfaces. the SL11R chip is ready for all the usb enumer- ation and download/program code. the SL11R internal masked rom (i.e. SL11R bios) is mapped from address 0xe800 to 0xffff. on power up or hardware reset, the SL11R processor jumps to the address of 0xfff0, which contains a long jump to the beginning of the internal rom of address 0xe800. see table 4-1 . 4.2 external rom: 0xc100-0xe800 the SL11R bios rom reserves addresses from 0xc100 to 0xe800 for external rom. during bios initialization, the SL11R will scan for the signature id (0xcb36) at location 0xc100. after a valid signature is detected, execution will begin at address 0xc 102 (see [ref. 1] SL11R_bios for more information). the signal nxromsel is used to enable the external rom. it is mapped from table 4-1. internal masked rom (SL11R bios) address memory description 0xe800-0xffef SL11R bios code/data space 0xfff0-0xfff3 jump to 0xe800 0xfff4-0xfff9 reserved for future use. 0xfffa-0xfffb rom bios checksum 0xfffc-0xfffd SL11R bios revision 0xfffe-0xfffe peripheral revision 0xffff-0xffff qt engine instruction revision
SL11R document #: 38-08006 rev. ** page 16 of 85 0xc100 to 0xe800 by default. however, the extended memory control can be used to configure multiple windows for external rom set-up. note : the address space from 0x8000-0xc100 can also be used as the external rom (see the external memory control set-up for more detail). 4.3 internal ram: 0x0000-0x0bff the SL11R contains a 1.5kx16 internal ram. this memory is used to buffer video data and usb packets and is accessed by the 16-bit processor and the sie (serial interface engine). usb transactions are automatically routed to the memory buffer. the 16- bit processor has the ability to set up pointers and block sizes in buffer memory for usb dma transactions. for example, video data can be read from the camera interface and is sent to the usb port by the internal dma engine. the SL11R bios uses this internal ram for usb buffers, bios variables and user data/code. executable code or data can reside in multiple locations: internal masked rom (3kx16), internal ram (3kx8), external rom and external sram. program code or data can also be loaded to either the internal or the external ram from the usb port, the rs232 port, or the 2-wire serial interface. the SL11R internal ram is mapped from 0x0000 to 0x0bff. see internal ram memory usage in table 2 below: note: 2. this address may be changed due to SL11R bios revision updates. the new SL11R bios may require more internal memory for its v ariable usage in any new SL11R bios. the addresses from 0x0000 to 0x00ff are reserved for hardware and software interrupt vectors (see [ref. 1] SL11R_bios for more information). addresses from 0x0100 to 0x01ff are reserved for internal register banks (SL11R register r0-r15 bank 0 and r0-r15 bank 1) and the software stack. others are reserved for usb control registers and other read/write control registers. addresses from 0x0200 to 0x021f are reserved for the hardware interrupt stack. addresses from 0x0220 to 0x0343 are available internal ram for application software. software can be downloaded via the usb port or uart interface (see [ref. 1] SL11R_bios for more information). 4.4 clock generator the SL11R has an option to use either a 48-mhz or 12-mhz external crystal or oscillator as its clock source. SL11R includes an internal pll that can be configured by software. at power-up, the SL11R bios default configuration sets the processor clock to run at 2/3 of x1 (of the external provided clock). example 1 changing SL11R cpu speed the default of the SL11R bios assumes a 48mhz input clock, so the SL11R processor clock is (2/3)*48mhz = 32mhz. see example below: mov [0xc006],0x10 ;clock = 2/3*x1 mov [0xc008],0 ;cpu clock at 32mhz if the x1 input clock is 48 mhz, then the maximum speed of the SL11R processor can be set at follows: mov [0xc006],0 ;clock = set up at x1 clock input mov [0xc008],0 ;cpu clock at 48mhz if the x1 input clock is 12 mhz, then the maximum speed of the SL11R processor can be set to: mov [0xc006],0x40 ;clock = 4*x1 mov [0xc008],0 ;cpu clock at 48mhz table 4-2. internal ram memory usage address memory description 0x0000 - 0x00ff hardware/software interrupts 0x0100 - 0x01ff register banks/usb control/software stack 0x0200 - 0x021f hardware interrupts stack 0x0220 - 0x0343 [2] SL11R bios internal buffers & variables 0x0344 - 0x0bff user ? s programming space
SL11R document #: 38-08006 rev. ** page 17 of 85 figure 4-1. 48-mhz crystal circuit figure 4-2. 12-mhz crystal circuit note: you need to set bit c2 =1 from configuration address (0xc006). see section 4.5 for cpu control speed. x1 cbk 0.01 f rf 1m rs 100 x1 48 mhz, series, 20-pf load cout 22 pf x2 lin 2.2 - 3.3 h x2 x1 rf 1m rs 2.7k x1 12 mhz, series, 20-pf load cout 22 pf cin 22 pf
SL11R document #: 38-08006 rev. ** page 18 of 85 4.5 usb interface the SL11R has a built-in transceiver that meets the usb specification v1.1. the transceiver connects directly to the physical l ayer of the usb engine. it is capable of transmitting or receiving serial data at the usb maximum data rate of 12 mbits/sec. the sl1 1r has four usb dma engines for four usb endpoints. each of the usb dma engines is independently responsible for its respective usb transaction. the 16-bit processor has the ability to set up pointers and block sizes in buffer memory for usb transactions. the SL11R controller contains a number of registers that provide overall control and status functions for usb transactions. the first set of registers is for control and status functions, while the second group is dedicated to specific endpoint functions. com- munication and data flow on the usb is implemented using endpoints. these uniquely identifiable entities are the terminals of communication flow between a usb host and usb devices. each usb device is composed of a collection of independently operating endpoints. each endpoint has a unique identifier: the endpoint number. (see usb specification v1.1. sec 5.3.1) the SL11R also includes the SL11R bios that provides a set of subroutines via interrupt calls for all usb interface functions required to communicate with a usb host (refer to [ref. 1] SL11R_bios for more information). the SL11R bios greatly simplifies the firmware/software development cycle. 4.5.1 usb global control & status register (0xc080: r/w) the usb global control & status register allows high-level control and provides status of the usb-dma engines. the global control & status register bits are defined as follows: d15-d4 reserved d0 ue usb enable = ? 1 ? , overall usb enable/disable bit d1 ur usb reset = ? 1 ? , usb received reset command d2 us usb sof = ? 1 ? , usb received sof command d3 ua usb activity = ? 1 ? , activity seen notes: suspend state should be entered if there is no activity after 3ms (ua). the us and ua bits are automatically cleared after they are read by the SL11R processor. d15-d4 are the reserved bits, should be written with zeros. the SL11R bios will set the ue=1 upon reset. 4.5.2 usb frame number register (0xc082: read only) the frame number register contains the 11-bit id number of the last sof received by the device from the usb host. d15-d11 reserved set to all zeros. d10-d0 s10-s0 sof id number of last sof received note: the SL11R bios uses this register to detect usb activity for the internal idle task. 4.5.3 usb address register (0xc084: r/w) address register holds the usb address of the device assigned by the host - initialized to address 0x0000 upon power up. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 000000000000uausurue d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 00000s10s9s8s7s6s5s4s3s2s1s0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 000000000a6a5a4a3a2a1a0
SL11R document #: 38-08006 rev. ** page 19 of 85 d15-d7 reserved set to all zeros d6-d0 a6-a0 usb address of device after assignment by host note: the SL11R bios modifies this register upon receiving the set_address from the host. (see [ref. 3] universal serial bus specification 1.1, chapter 9 for more information) 4.5.4 usb command done register (0xc086: write only) this is the usb command done register. it is only used by the control point (endpoint 0). d15-d1 reserved set to all zeros. d0 e set e=0 for successful command completion set e=1 for error command completion note: the SL11R bios modifies this register upon command completion on endpoint 0. 4.6 usb endpoint 0 control & status register (0xc090: r/w) see the usb endpoint 3 control & status register for more information. 4.7 usb endpoint 1 control & status register (0xc092: r/w) see the usb endpoint 3 control & status register for more information. 4.8 usb endpoint 2 control & status register (0xc094: r/w) see the usb endpoint 3 control & status register for more information. 4.9 usb endpoint 3 control & status register (0xc096: r/w) 4.9.1 general description for all endpoints from endpoint 0 to endpoint 3 the SL11R controller supports four endpoints. endpoint 0 is the default pipe and is used to initialize and control the peripher al device. it also provides access to the peripheral device's configuration information, and supports control transfers. endpoint 1, 2, and 3 support interrupt transfers, bulk transfers up to 64 bytes/packet, or isochronous transfers up to 1024 bytes/packet size. 4.9.2 usb endpoints control (for writing) each of the endpoint control registers when written have the following functions assigned: d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 000000000000000e bit position bit name function d0 arm allows enabled transfers when set to '1'. cleared to '0' when transfer is complete d1 enable when set to ? 1 ? it allows transfers to this endpoint. when set to '0' usb transactions are ignored. if enable = '1' and arm = '0', the endpoint will return nak to usb transmissions. d2 dir when set to ? 1 ? , it transmits to host (in). when '0' receive from host (out) d3 iso when set to '1' it allows isochronous mode for this endpoint d4 stall when set to ? 1 ? it sends stall in response to next request on this endpoint d5 zero length when set to ? 1 ? it sends a zero length packet d6-d15 not defined set to logic ? 0 ? s
SL11R document #: 38-08006 rev. ** page 20 of 85 4.9.3 usb endpoints status (for reading) reading the endpoint status register provides status information relative to the packet that has been received or transmitted. the register is defined as follows: notes: endpoint 0 is set up as a control endpoint. the dir bit is read-only, and indicates the direction of the last completed transaction. if the direction is incorrect, it is the firmware ? s responsibility to handle the error. on other endpoints, dir bit is written, and if the direction of the transfer does not match the dir bit, then the transaction is ignored. at the end of any transfer to an armed and enabled endpoint (with the correct dir bit), an interrupt occurs, and vectors to a different location depending upon whether an error occurred or not. at the end of this transfer, the corresponding endpoint is disarmed (the arm bit is cleared), and the data0/data1 toggle bit is advanced if no error occurred. if a packet is received wit h an incorrect toggle state, the packet is ignored so that the host will re-send the data. the data0/data1 bit is automatically toggled by the hardware. to reset this data0/data1 toggle bit to data0, the enable on the d1 bit should be cleared to ? 0 ? and then set to ? 1 ? . when the zero length bit (d5) is set, the host will receive the zero length usb packet, regardless of the number of bytes in the usb count register. the SL11R bios has full control of usb endpoint 0. the SL11R bios responds to all numeration from the host. on other endpoints, the SL11R bios can be used to control under bios interrupt calls (see [ref. 1] SL11R_bios). the SL11R bios will set all usb control & status registers for endpoint 1 through 3 to zero upon receiving the set_config command from host. (see [ref. 3] universal serial bus specification 1.1 1, chapter 9 for more information.) 4.9.4 usb endpoint 0 address register (0x0120: r/w) this is the pointer to memory buffer location for usb reads and writes to this endpoint. at the end of any transfer, this regis ter will contain its original value plus the value in the usb endpoint count register. 4.9.5 usb endpoint 1 address register (0x0124: r/w) see usb endpoint 0 address register (0x0120: r/w) 4.9.6 usb endpoint 2 address register (0x0128: r/w) see usb endpoint 0 address register (0x0120: r/w) 4.9.7 usb endpoint 3 address register (0x012c: r/w) see usb endpoint 0 address register (0x0120: r/w) 4.9.8 usb endpoint 0 count register (0x0122: r/w) this register is used to set the maximum packet size for the usb transfer. at the end of a successful transfer, the usb endpoin t count register is set to zero. 4.9.9 usb endpoint 1 count register (0x0126: r/w) see usb endpoint 0 count register (0x0122: r/w) 4.9.10 usb endpoint 2 count register (0x012a: r/w) see usb endpoint 0 count register (0x0122: r/w) bit position bit name function d0 arm if '1', the endpoint is armed d1 enable if '1', the endpoint is enabled d2 dir direction bit. if '1', set to transmit to host (in). if '0', set to receive from host (out) d3 iso if ? 1 ? , isochronous mode selected for this endpoint d4 stall if '1', endpoint will send stall on usb when requested d5-d12 not used read returns logic ? 0 ? s d13 setup if '1', a setup packet has been received d14 error if '1', an error condition occurred on last transaction for this endpoint d15 done if '1', transaction completed. arm bit is cleared to '0' when done set
SL11R document #: 38-08006 rev. ** page 21 of 85 4.9.11 usb endpoint 3 count register (0x012e: r/w) see usb endpoint 0 count register (0x0122: r/w) 4.10 processor control registers the SL11R provides software control registers that can be used to configure the chip mode, clock control, read software version and software breakpoint control. 4.10.1 configuration register (0xc006: r/w) the configuration register is used to configure the SL11R into the appropriate mode, and to select a clock multiplier. note: d6-4 and c2-0 are clock configuration bits. these bits select the clock source. the clock may come from an outside pin (x1 or x_pclk) or it may come from the pll multiplier as indicated in the table. d3 cd if clock disable bit = ? 1 ? , this clock configuration register can no longer be modified through software writes. it is a ? sticky bit ? used to lock the configuration through a write to this bit in the boot prom code. note : on the SL11R chip set, this bit will be set to zero. `there are four modes defined in this documentation: dvc 8-bit dma mode, fast epp mode, 8/16-bit dma mode and general purpose io (gpio) mode. all modes are pin-compatible. d2, d1 m1,m0: SL11R modes are selected as shown here: d0 md if mode disable bit = ? 1 ? , this configuration register can no longer be modified through software writes. it is a ? sticky bit ? used to lock the configuration through a write to this bit in the boot prom code. note : by default, this bit will be set to zero by the SL11R bios. d15-d7 reserved should be set to all zeros. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 000000000c2c1c0cdm1m0md c2 c1 c0 pclk rclk oe 0 0 0 x1 x1 0 0 0 1 2/3*x1 x1 0 0 1 0 x_pclk x1 0 0 1 1 2/3*x1 x1 1 1 0 0 4*x1 4*x1 0 1 0 1 8/3*x1 4*x1 0 1 1 0 4*x1 4*x1 1 1 1 1 8/3*x1 4*x1 1 m1 m0 mode 00 gpio 0 1 dvc 8-bit dma 1 0 fast epp 11 8/16-bit dma
SL11R document #: 38-08006 rev. ** page 22 of 85 where: pclk is connected to the SL11R processor clock. rclk is the resulting clock that connects to other modules (i.e. pwm, usb engine). oe when oe =1, the x_pclk (pin 59) will become an output pin of the pclk value. notes: when the x1 input pin is fed with a 12 mhz signal, the software should set c2 to ? 1 ? to enable the pll. x_pclk is a bidirectional pin allowing an additional clock input for pclk when selected or an observation pin for pclk when oe = ? 1 ? . the x_pclk can be used as the input clock like x1, but only when mode c2=0, c1=1, c0=0. upon reset, the SL11R bios will set this register equal to 0x0010 (i.e. c2=0, c1=0, c0=1, pclk=x1, rclk=x1, oe=0, m1-m0=0=gpio mode). 4.10.2 speed control register (0xc008: r/w) the speed control register allows the SL11R processor to operate at a number of speed selections. a four-bit divider (spd3-0 + 1) selects the speed as shown below. speed will also depend on the clock multiplier. see configuration register (0xc006: r/w) for more information. d3-d0 spd3-spd0 speed selection bits d15-d4 reserved should be set to all zeros. note: upon reset, the lowest speed is selected for low power operation. the SL11R bios will configure the clock to 24mhz as part of its initialization. d15-d4 d3 d2 d1 d0 0 spd3 spd2 spd1 spd0 spd3-0 SL11R speed 0000 48.00 mhz. 0001 24.00 mhz. 0010 16.00 mhz. 0011 12.00 mhz. 0100 09.60 mhz. 0101 08.00 mhz. 0110 06.86 mhz. 0111 06.00 mhz. 1000 05.33 mhz. 1001 04.80 mhz. 1010 04.36 mhz. 1011 04.00 mhz. 1100 03.69 mhz. 1101 03.42 mhz. 1110 03.20 mhz. 1111 03.00 mhz.
SL11R document #: 38-08006 rev. ** page 23 of 85 4.10.3 power down control register (0xc00a: r/w) during power down mode, the peripherals are put in a ? pause ? state. all counters and timers stop incrementing and the pwm stops. there are two ways to enter power-down mode: suspend or halt . d5 usb enable restarts on usb transition resulting in device power up. d4 gpio enable restarts on gpio transition resulting in device power up (see gpio interrupt control register (0xc01c:r/w)). d3-d2 pud1-pud0 power up delay selection . four delays are provided and selected using these select bits. this is time from power up until processor starts executing allowing clock to settle. d1 suspend to save power, suspend mode stops all clocks in the SL11R. this mode ends with a transition on either usb or any interrupt. it is followed by a delay set in the power-up delay bit fields . d0 halt ends with an interrupt. d15-d6 reserved should be set to all zeros. 4.10.4 breakpoint register (0xc014: r/w) the breakpoint register holds the breakpoint address. access to this address causes an int127. d15-0 a15-0 breakpoint address. 4.11 interrupts the SL11R provides 127 interrupt vectors. the first 64 vectors are hardware interrupts and the next 64 are software interrupts (see the [ref. 1] SL11R_bios for more information). d15-d6 d5 d4 d3 d2 d1 d0 0 usb gpio pud1 pud0 suspend halt pud1 pud0 power-up delay 0 0 0 milliseconds 0 1 1 milliseconds 1 0 8 milliseconds 1 1 64 milliseconds d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0
SL11R document #: 38-08006 rev. ** page 24 of 85 4.11.1 hardware interrupts the SL11R allocates addresses from 0x0000 to 0x003e for hardware interrupts. the hardware interrupt vectors are shown below: notes: 3. these hardware interrupt vectors are reserved for internal SL11R-bios usage. you should not attempt to overwrite these function s. 4. these hardware interrupt vectors are initialized to return on the interrupt. 5. the sof interrupt is generated when there is an incoming sof on the usb. all these vector interrupts are read/write accessible. you can overwrite these default software interrupt vectors by replacing your interrupt service subroutine. the addresses from 0x0000 to 0x003e are read/write accessible and can be used for variables. 4.11.2 interrupt enable register (0xc00e: r/w) this is a global hardware interrupt enable register that allows control of the hardware interrupt vectors. the SL11R bios defau lt set-up of this register is 0x28 (i.e. usb and uart bits are set). d6 mbx mail box interrupt enable (8/16-bit dma mode only) d5 usb usb interrupt enable d4 fdma fast dma done interrupt enable d3 uart uart interrupt enable table 4-3. hardware interrupt table interrupt number vector address interrupt type 00x0000timer0 [3] 10x0002timer1 [4] 20x0004gp irq0 [4] 30x0006gp irq1 [4] 40x0008uart tx [3] 50x000auart rx [3] 6 0x000c fast dma done [4] 7 0x000e usb reset 8 0x0010 usb sof [5] 9 0x0012 usb endpoint0 no error [3] 10 0x0014 usb endpoint0 error [3] 11 0x0016 usb endpoint1 no error 12 0x0018 usb endpoint1 error 13 0x001a usb endpoint2 no error 14 0x001c usb endpoint2 error 15 0x001e usb endpoint3 no error 16 0x0020 usb endpoint3 error 17 0x0022 8/16-bit dma mode mailbox tx empty [4] 18 0x0024 8/16-bit dma mode mailbox rx full [4] 19-63 0x0026- 0x003e reserved ? d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 000000000mbxusbfdmauartgpt1t0
SL11R document #: 38-08006 rev. ** page 25 of 85 d2 gp general purpose i/o pins interrupt enables (see gpio interrupt control register (0xc01c: r/w)) d1 t1 timer1 interrupt enable d0 t0 timer0 interrupt enable 4.11.3 gpio interrupt control register (0xc01c: r/w) this register defines the polarity of the gpio interrupt on irq1 (gpio25) and irq0 (gpio24). the gpio bit on the interrupt enable register must be set in order for this register to operate. d3 p1 irq1 polarity is rising edge if ? 1 ? , falling edge if ? 0 ? d2 e1 enable irq1 if set to ? 1 ? d1 p0 irq0 polarity is rising edge if ? 1 ? , falling edge if ? 0 ? d0 e0 enable irq0 if set to ? 1 ? note: the interrupts can be enabled for ? suspend mode ? by the power down register or enabled for interrupts by the interrupt enable register. 4.11.4 software interrupts the SL11R allocates addresses from 0x0040 to 0x00fe for software interrupts. the software interrupt vectors are shown in table 4-4 : d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 000000 000000p1e1p0e0
SL11R document #: 38-08006 rev. ** page 26 of 85 notes: 6. these software vectors are reserved for the internal SL11R-bios. the user should not overwrite these functions. 7. these vectors are used as the data pointers. the user should not execute code (i.e. jmp or int ) to these vectors. see [ref. 1] SL11R_bios for more information. table 4-4. software interrupt table interrupt number vector address interrupt type 64 (0x40) 0x0080 2-wire serial interface_int [6] 65 (0x41) 0x0082 reserved for future extension of other serial eeprom 66 (0x42) 0x0084 uart_int [6] 67 (0x43) 0x0086 scan_int [6] 68 (0x44) 0x0088 alloc_int [6] 69 (0x45) 0x008a data: start of free memory. default=0x200 [7] 70 (0x46) 0x008c idle_int 71 (0x47) 0x008e idler_int 72 (0x48) 0x0090 insert_idle_int 73 (0x49) 0x0092 pushall_int [6] 74 (0x4a) 0x0094 popall_int [6] 75 (0x4b) 0x0096 free_int [6] 76 (0x4c) 0x0098 redo_arena [6] 77 (0x4d) 0x009a hw_swap_reg [6] 78 (0x4e) 0x009c hw_rest_reg [6] 79 (0x4f) 0x009e scan_decode_int 80 (0x50) 0x00a0 usb_send_int [6] 81 (0x51) 0x00a2 usb_receive_int [6] 82 (0x52) 0x00a4 reserved 83 (0x53) 0x00a6 usb_standard_int 84 (0x54) 0x00a8 data: standard loader vector. defaut=0 [7] 85 (0x55) 0x00aa usb_vendor_int 86 (0x56) 0x00ac data: usb_vendor loader. default = 0xff [7] 87 (0x57) 0x00ae usb_class_int 88 (0x58) 0x00b0 data: usb_class_loader. default = 0 [7] 89 (0x59) 0x00b2 usb_finish_int 90 (0x5a) 0x00b4 data: device descriptor. default = cypress device desc [7] 91 (0x5b) 0x00b6 data: configuration desc. default = cypress configuration [7] 92 (0x5c) 0x00b8 data: string descriptor. default = cypress string desc. [7] 93 (0x5d) 0x00ba usb_parse_config_int 94 (0x5e) 0x00bc usb_loader_int 95 (0x5f) 0x00be usb_delta_config_int 96 (0x60) 0x00c0 usb_pullup_int 97 - 104 0xc2-0xd0 reserved for future addition secondary usb port 105 (0x69) 0x00d2 power_down_subroutine 106-109 0xd4-0xda reserved for future secondary usb port 110-124 0xde-0xf8 user ? s isr or internal peripheral interrupt 125-127 0xfa-0xfe reserved for the debugger
SL11R document #: 38-08006 rev. ** page 27 of 85 all these vector interrupts are read/write accessible. user can overwrite these default software interrupt vectors by replacing the user ? s interrupt service subroutine. 4.12 uart interface. the SL11R controller uart port supports a range of baud rates from 900 baud up to 115.2k baud. baud rate selection is made in the uart control register. buffer status can be monitored in the uart status register. transmit and receive data is written or read from the uart data register. the uart timers are independent of the general-purpose timers. the uart will cause ? edge trigger ? type interrupts when the receive buffer becomes full or the transmit buffer becomes empty. the SL11R bios uses the uart port for the software debugging process. it is recommended that the user include this interface in their hardware design. a simple 4-pin header may be used to connect to a serial cable equipped with a max202 transceiver. figure 4-3. uart port connection the SL11R bios uses gpio28 for data transmit (tx) and gpio27 for data receive (rx). these two pins cannot be used for any other purpose. note : on reset, the SL11R bios will configure the uart to operate at 14,400 baud. other parameters are: 1 stop bit, 8 data bits, no parity. 4.12.1 uart control register (0xc0e0: r/w) the SL11R allocates two general purpose i/o signals for the uart function. they are gpio28 (uart_txd) and gpio27 (uart_rxd). on reset, the SL11R bios will default this register to the value of 0x000b (i.e. uart enable and baud = 14.4k baud). d15-d5 reserved bits set to all zeros. d4 div8 acts as a pre-scaler if set to ? 1 ? , divides the clock by 8 before generating the uart clock. d3-1 b2-0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 00000000000div8b2b1b0e baud rate selector bits. with /8 prescaler 000 115.2k baud 14.4k baud 001 57.6k baud 7.2k baud 010 38.4k baud 4.8k baud 011 28.8k baud 3.6k baud 100 19.2k baud 2.4k baud 101 14.4k baud 1.8k baud 110 9.6k baud 1.2k baud 111 7.2k baud 0.9k baud 7; *1' 5; vcc *3,2 *1' *3,2 9&& !"##
SL11R document #: 38-08006 rev. ** page 28 of 85 d0 e enable uart when set = ? 1 ? . when ? 0 ? uart pins are gpio. 4.12.2 uart status register (0xc0e2: read only) this register is used by the SL11R bios to detect the uart status function via rxf and txe flags. d15-d2 reserved bits set to all zeros. d1 rxf receive buffer full flag. d0 txe transmit buffer empty flag. set to ? 1 ? when data moves from buffer to output shift register. note: no error detection for received data is supported. 4.12.3 uart transmit data register (0xc0e4: write only) this register is used by the SL11R bios to send data to the host. d7-d0 tr7-0 uart transmit data 4.12.4 uart receive data register (0xc0e4: read only) this register is used by the SL11R bios to receive data from the host. d7-d0 rd7-0 uart receive data. 4.13 serial eeprom interface (2-wire serial interface) the SL11R provides an interface to an external serial eeprom. the interface is implemented using general purpose i/o signals. a variety of serial eeprom formats can be supported: currently the bios rom supports the two-wire serial eeprom type. the serial eeprom can be used to store specific peripheral usb configuration and add on value functions. it can also be used for field product upgrades the SL11R bios uses an interrupt to read and write from/to an external serial eeprom. the recommended serial eeprom device is a 2-wire serial cmos eeprom (at24cxx device family). currently, the SL11R bios revision 1.1 allows reading/writ- ing to/from eeprom, up to 2k bytes (16k bits), 2-wire serial interface device (i.e. at24c16). the user ? s program and usb vendor/device configuration can be programmed and stored into the external eeprom device. on power up the content of the eeprom will be downloaded into ram and may be executed as code or used as data, or both. the advantage of the 2-wire serial interface/eeprom interface is the space and cost saving when compared to using an external 8-bit prom/eprom. the SL11R bios uses two gpio pins, gpio31 and gpio30 to interface to an external serial eeprom (see figure 4-4 ): gpio31 is connected to the serial clock input (scl). gpio30 is connected to the serial data (sda). we recommend you add a 5k to 15k pull-up resistor on the data line (e.g. gpio30). d15-d7 d6 d5 d4 d3 d2 d1 d0 0 00000rxftxe d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 00000000tr7tr6tr5tr4tr3tr2tr1tr0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0
SL11R document #: 38-08006 rev. ** page 29 of 85 pin 1 (a0), pin 2 (a1), pin 3 (a2), pin 4 (gnd) and pin 7 write protect) are connected to ground. figure 4-4. 2-wire serial interface 2k-byte connection the current SL11R bios only support up to a 2kbyte serial eeprom. to read and write to a device that is larger than 2kbytes, the SL11R-bios requires additional serial eeprom to be connected as shown in figure 4-5 . figure 4-5. 2-wire serial interface 16k connection in this example, the SL11R bios will first access the (small) program residing on ic1 serial eeprom, and then it will access the second ic2 eeprom (see [ref. 1] SL11R_bios for more information). 4.14 external sram, eprom, dram the SL11R has a multiplexed address port and 16-bit data port. these interface signals are provided to interface to an external sram, rom or dram. the dram port provides ras, cas, rd and wr control signals for data access and refresh cycles to the dram. at boot up stage, the SL11R bios configures the SL11R for external sram and serial eeprom. in addition, the external memory interface is set up as 16-bit and 7 wait states for both external sram and eeprom. the dram controller needs to be set up by the user. example 2 SL11R extended memory setup: internal_rom_start: mov [0xc03a],0x0077 ;set 16-bit rom & 7 wait cmp [0xc100],0xcb36 ;check for special pattern in external rom je 0xc102 ;if it ? s there, jump to it mov [0xc006],0x10 ;2/3 clock mov [0xc008],1 ;at 24 mhz mov [0xc03e],3 ;extra wait state for rom and debug cmp [0xc100],0xc3b6 ;external rom has 0xc3b6 as first 16 bits je xrom_ok cmp b[0xc100],0xb6 ;check 0xc3b6 for 8-bit rom jne xrom_ok or [0xc03a],0x80 ;set for 8-bit rom eeprom 0.1uf vcc 5k gpio30 at24c16 1 2 3 4 8 7 6 5 a0 a1 a2 gnd vcc wp scl sda gpio31 gpio31 0.1uf 5k gpio30 vcc eeprom at24c128 1 2 3 4 8 7 6 5 a0 a1 a2 gnd vcc wp scl sda
SL11R document #: 38-08006 rev. ** page 30 of 85 xrom_ok : mov [0xc00],0xc3b6 ;check 0xc3b6 for 16-bit ram cmp [0xc00],0xc3b6 je xram_ok or [0xc03a],8 ;set for 8-bit external ram xram_ok: note: the external memory devices can be 8 or 16 bits wide, and can be programmed to have up to 7 wait-states. external sram/prom requires one wait state. 4.14.1 memory control register (0xc03e: r/w) this register provides control of wait states for the internal ram and rom. d2 ra if ? 1 ? , one-wait state for internal ram is added d1 ro if ? 1 ? , one-wait state for internal rom is added d0 db if ? 1 ? , debug mode is enabled. internal address bus is echoed to external address pins. 4.14.2 extended memory control register (0xc03a: r/w) this register provides control of wait states for the external sram/dram/eprom. d12 rm rom merge. if ? 1 ? , nxromsel is active if nxmemsel is active. d11 em3 extended memory width ('0' = 16, '1' = 8) d10-8 em2-0 extended memory wait states (0 - 7) d7 ro3 external rom width ('0' = 16, '1' = 8) d6-4 ro2-0 external rom wait states (0 - 7) d3 ra3 external ram width ('0' = 16, '1' = 8) d2-0 ra2-0 external ram wait states (0 - 7) note: the default wait state setting on power up or reset is 7 wait states. 4.14.3 extended page 1 map register (0xc018: r/w) this register contains the page 1 high order address bits. these bits are always appended to accesses to the page 1 memory mapped space. the default is 0x0000. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 000000 0000000rarodb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 rm em3 em2 em1 em0 ro3 ro2 ro1 ro0 ra3 ra2 ra1 ra0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0000000a21a20a19a18a17a16a15a14a13
SL11R document #: 38-08006 rev. ** page 31 of 85 if bit a21 is ? 1 ? , page 1 reads/writes will access external dram if bit a21 is ? 0 ? page 1 reads/writes will access some other external area (sram, rom or peripherals). nxmemsel will be the external chip select for this space. d8-0 a21-13 page 1 high order address bits. the address pins on a21-a13 will reflect the content of this register when SL11R accesses the address 0x8000-0x9fff. 4.14.4 extended page 2 map register (0xc01a: r/w) this register contains the page 2 high order address bits. these bits are always appended to accesses to the page 2 memory mapped space. the default is 0x0000. if bit a21 is ? 1 ? , page 2 reads/writes will access external dram if bit a21 is ? 0 ? page 2 reads/writes will access some other external area (sram, rom or peripherals) and nxmemsel will be the external chip select for this space. d8-0 a21-13 page 2 high order address bits. the address pins on a21-a13 will reflect the content of this register when SL11R access the address 0xa000-0xbfff. 4.14.5 dram control register (0xc038: r/w) a multiplexed address port and 16-bit data port are provided to interface to an external 256kx16 or a 1megx16 edo dram. the port provides nras, ncasl, ncash, ndramwr and ndramoe control signals for data access and refresh cycles to the dram. this register is designed to control the dram interface. d2 dt dram turbo, enable when set = '1'. uses 1 clock for cas instead of 2. d1 pe dram page mode enable when set = '1'. d0 re dram refresh enable when set = '1'. note: most of edo and page mode dram can be used as long as the cas signal is issued before the ras signal. page mode access allows multiple cas addresses to be issued within 1 row address. the page really corresponds to the row. once the row address has been accessed, any accesses to that page can be made without issuing the row address again. only the column address is necessary. this allows for faster read and write accesses to the same page. 4.14.6 memory map the total memory space allocated by the SL11R is 64k-bytes. program, data, and i/o space are contained within a 64k-byte address space. the program code or data can be stored in either external ram or external rom. the SL11R allows extended data (video) to be stored on an external edo dram. the entire (video image) data can be transferred via dma directly to dram without software intervention. the total dma size can be up-to 2m-bytes. the SL11R processor can access dram data via the address space from 0x8000 to 0xbfff . the SL11R controller provides a 16-bit memory interface that can support a wide variety of external dram, ram and rom devices. the SL11R controller memory space is byte addressable and is divided as follows: d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0000000a21a20a19a18a17a16a15a14a13 d15-d7 d6 d5 d4 d3 d2 d1 d0 0 0000dtpere
SL11R document #: 38-08006 rev. ** page 32 of 85 each external memory space can be 8 or 16 bits wide, and can be programmed to have up to 7 wait-states. notes: 8. the external ram address from 0x0000 to 0x0c00 will not be accessible from the SL11R processor. this is an overlay memory space between internal ram and external ram. the addressable external ram will occupy from 0x0c00-0x7fff, which is 29k-byte. the signal name nxramsel on s l11r-pin56 will be active when the cpu access address from 0x0c00 to 0x7fff. 9. when bit 12 (rom merge bit) of the extended memory controller register at address 0xc03a is ? 0 ? , then the external rom address space will be mapped from 0xc100 to 0xe7ff. the address from 0x8000 to 0xc100 and the address from 0xe800 to 0xffff are the overlay memory spaces. the ac tual total size of the external rom will be (0xe800-0xc100), which is 9.75k-byte. the signal nxromsel on the SL11R (pin57) will be active when the cpu accesses the address from 0xc100 to 0xe7ff. the signal nxmemsel on the SL11R (pin58) will be active when the cpu accesses the address from 0x8000 to 0xbfff. when bit 12 (rom merge bit) of the extended memory controller register at address 0xc03a is ? 1 ? , then the external rom address space will be mapped into these windows: 0x8000 to 0xbfff and 0xc100 to 0xe7ff. the address from 0xc000 to 0xc100 and the address from 0xe800 to 0xffff are the overlay memory spaces. the actual total size of the external rom will be (0xc000-0x8000) and (0xe800-0xc100), which is 16k-byte + 9.75k-bytes, or 25.75k. table 4-5. memory map function address internal ram 0x0000 ? 0x0bff external ram 0x0c00 ? 0x7fff [8] extended page 1/dram 0x8000 ? 0x9fff extended page 2/dram 0xa000 ? 0xbfff memory mapped registers 0xc000 ? 0xc0ff external rom 0xc100 ? 0xe7ff [9] internal rom 0xe800 ? 0xffff unused overlay memory space 0x0000 to 0x0c00 actual external ram 0x0c00 to 0x7fff sram (16kx16) or bit 12 (rom merge) of the extended memory controller register = 0 bit 12 (rom merge) of the extended memory controller register = 1 actual external rom 0xc100 to 0xe7ff rom (16kx16) or actual external rom 0x8000 to 0xbfff unused overlay memory space 0x8000 to 0x9fff actual external rom 0xc100 to 0xe7ff rom (16kx16) or unused overlay memory space 0xa000 to 0xbfff unused overlay memory space 0xc000 to 0xc0ff unused overlay memory space 0xc000 to 0xc0ff
SL11R document #: 38-08006 rev. ** page 33 of 85 4.15 general timers and watch dog timer the SL11R controller has two built in programmable timers that can provide an interrupt to the SL11R engine. the timers decrement on every microsecond clock tick. an interrupt occurs when the timer reaches zero. 4.15.1 timer 0 count register (0xc010: r/w) the SL11R bios uses the timer 0 for time-out function and power down mode. at the end of the power up, the SL11R bios disables the timer 0 interrupt. if you wish to use timer 0 for power down function, see the [ref. 1] SL11R_bios for more information. d15-0 t15-0 timer count value. 4.15.2 timer 1 count register (0xc012: r/w) the SL11R timer 1 is for user applications. the SL11R bios does not use this timer. d15-0 t15-0 timer count value 4.15.3 watchdog timer count & control register (0xc00c: r/w) the SL11R provides a watchdog timer to monitor certain activities. the watchdog timer can also interrupt the SL11R processor. the default value of this register is 0x0000. d5 wt watchdog time-out occurred. d4-3 to1-0 time-out count: 00 01 milliseconds 01 04 milliseconds 10 16 milliseconds 11 64 milliseconds d2 ep enable permanent wd timer. if set = ? 1 ? wd timer is always enabled. cleared only on reset. d1 enb enable wd timer operation when = ? 1 ? . d0 rc reset count. when set = ? 1 ? . notes: you must assert reset count (rc), before time-out occurs to avoid watchdog trigger the watchdog timer overflow causes an internal processor reset. the processor can read the wt bit after exiting reset to determine if the wt bit is set. if it is set, a watchdog time-out occurred. the wt value will be cleared on the next external reset. 4.16 special gpio function for suspend, resume and low-power modes the SL11R cpu supports suspend, resume and cpu low power modes. the SL11R bios assigns gpio29 for the usb data+ line pull-up (this pin can simulate usb cable removal or insertion while usb power is still applied to the circuit) and the gpi o20 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 t15 t14 t13 t12 t11 t10 t9 t8 t7 t6 t5 t4 t3 t2 t1 t0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 t15 t14 t13 t12 t11 t10 t9 t8 t7 t6 t5 t4 t3 t2 t1 t0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0000000000wtto1to0enbeprc
SL11R document #: 38-08006 rev. ** page 34 of 85 for controlling power off function. the gpio20 can be used for device low power mode; it will remove power from the peripherals in suspend mode. once usb power is restored, the power to the peripherals may be enabled. the SL11R bios will execute the pull up interrupt upon power-up. to use this feature, the gpio29 pin must be connected to the data+ line of the usb connector (see figure below). for more information about this function, see the [ref. 1] SL11R_bios. figure 4-6. special gpio pull-up connection example 4.17 programmable pulse/pwm interface the SL11R controller supports four programmable digital pulse output channels. these channels can also be used for pulse width modulation (pwm) operation. operation is directed by the pwm control register, maximum count register, and the individual start and stop counter registers. these are provided for each of the four output channels. to set up pwm operation, the maximum count register is set to the desired maximum count value. then the start and stop value for each channel is written with the required values. the start and stop values are chosen to achieve the desired pulse widths during each cycle. when the channels are disabled (by the control register), the associated i/o pins revert to gpio use. figure 4-7. pwm block diagram note : the rclk is the resulting clock (see the speed control register (0xc006: r/w)). 4.17.1 pwm control register (0xc0e6: r/w) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 st 0 0 0 sc2 sc1 sc0 os p3 p2 p1 p0 en3 en2 en1 en0 usb type b connector 1 2 3 4 v cc d- d+ gnd 33 ? 33 ? gpio29 1.5 k ? pwm block diagram
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SL11R document #: 38-08006 rev. ** page 35 of 85 d15 st start bit. set to ? 1 ? to begin operation. ? 0 ? stops operation d14-12 reserved always ? 0 ? ? s. d11-9 sc2-0 prescaler value selection d8 os enable one shot mode for pwm channels. one shot mode runs the number of counter cycles set in the pwm cycle count register and then stops. the default is continuous repeat. d7-d4 p3-0 individual polarity bits for channels 3 - 0. ? 1 ? is active high or rising edge pulse. d3-d0 en3-0 individual enable bits for channels 3 - 0. ? 1 ? enables. notes: if not enabled, i.e., if set is '0', the pins become gpio. to force the outputs to ? 0 ? or ? 1 ? : if start register = stop register, then output stays at ? 0 ? if stop register > max count register, then output stays at ? 1 ? 4.17.2 pwm maximum count register (0xc0e8: r/w) d15-10 reserved always '0' 's. d9-0 c9-c0 maximum count value. 4.17.3 pwm channel 0 start register (0xc0ea: r/w) d15-10 reserved always '0' 's. d9-0 s9-s0 start count for pwm channel 0. sc2-0 freq. 000 48.00 mhz 001 24.00 mhz 010 06.00 mhz 011 01.50 mhz 100 375 khz 101 93.80 khz 110 23.40 khz 111 05.90 khz d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 000000c9c8c7c6c5c4c3c2c1c0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 000000s9s8s7s6s5s4s3s2s1s0
SL11R document #: 38-08006 rev. ** page 36 of 85 4.17.4 pwm channel 0 stop register (0xc0ec: r/w) d15-10 reserved always ? 0 ? ? s. d9-0 s9-s0 stop count for pwm channel 0. 4.17.5 pwm channel 1 start register (0xc0ee: r/w) d15-10 reserved always ? 0 ? ? s. d9-0 s9-s0 start count for pwm channel 1. 4.17.6 pwm channel 1 stop register (0xc0f0: r/w) d15-10 reserved always ? 0 ? ? s. d9-0 s9-s0 stop count for pwm channel 1. 4.17.7 pwm channel 2 start register (0xc0f2: r/w) d15-10 reserved always ? 0 ? ? s. d9-0 s9-s0 start count for pwm channel 2. 4.17.8 pwm channel 2 stop register (0xc0f4: r/w) d15-10 reserved always ? 0 ? ? s. d9-0 s9-s0 stop count for pwm channel 2. 4.17.9 pwm channel 3 start register (0xc0f6: r/w) d15-10 reserved always ? 0 ? ? s. d9-0 s9-s0 start count for pwm channel 3. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 000000s9s8s7s6s5s4s3s2s1s0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 000000s9s8s7s6s5s4s3s2s1s0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 000000s9s8s7s6s5s4s3s2s1s0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 000000s9s8s7s6s5s4s3s2s1s0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 000000s9s8s7s6s5s4s3s2s1s0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 000000s9s8s7s6s5s4s3s2s1s0
SL11R document #: 38-08006 rev. ** page 37 of 85 4.17.10 pwm channel 3 stop register (0xc0f8: r/w) d15-10 reserved always ? 0 ? ? s. d9-0 s9-s0 stop count for pwm channel 3. 4.17.11 pwm cycle count register (0xc0fa: r/w) d15-0 c15-0 number of cycles to run in one-shot mode (0-64k) the os bit in the pwm control register must be set. note: number of os cycles to run = c+1. example for 1 cycle, set c=2 4.18 fast dma mode this mode is currently used by the dvc 8-bit dma and 8/16-bit dma modes. in dvc 8-bit dma mode, the dma data path will be 8, which corresponds to sd7-sd0. in the 8/16-bit dma mode, the dma data path can be configured as either 8 or 16. 4.18.1 dma control register (0xc02a: r/w) external device data presented to s15-sd0/sd7-sd0 is automatically written into the ram of the SL11R, under fast dma control. the dma must be enabled in the dma control and address register. d2 tsz transfer size. 8 bit when set to ? 1 ? , 16-bit when set to ? 0 ? d1 dir dma direction. when set to ? 0 ? , data transfers from peripheral to memory. when set to '1 ? memory to peripheral. d0 dma dma enabled when set to '1'. bit clears to ? 0 ? when dma is done. note for dvc 8-bit dma mode: set transfer size to 16 bits for the dvc 8-bit dma mode. set dma direction for peripheral to memory for dvc 8-bit dma mode. 4.18.2 low dma start address register (0xc02c: r/w) this register contains the low order word of the starting dma address. d15-0 a15-a0 low 16 bits of dma address d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 000000s9s8s7s6s5s4s3s2s1s0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 c15 c14 c13 c12 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 d7 d6 d5 d4 d3 d2 d1 d0 00000tszdirdma d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0
SL11R document #: 38-08006 rev. ** page 38 of 85 4.18.3 high dma start address register (0xc02e: r/w) this register contains the high order word of the starting dma address. d5-d0 a21-a16 high address bits for dma start address note: a21 = 1 the starting memory address will be in the dram. the a21 bit in the high dma stop address register must match this bit. 4.18.4 low dma stop address register (0xc030: r/w) this register contains the low order word of the stopping SL11R memory address. this is the last dma address in memory. dma will stop when this address is reached and if the fdma bit in the interrupt enable register (0xc00e: r/w) is enabled, an interrupt will also be generated. d15-0 a15-a0 low 16 bits of the dma stop address 4.18.5 high dma stop address register (0xc032: r/w) this register contains the high order word of the stopping SL11R memory address. this is the last dma address in memory. dma will stop when this address is reached. d5-d0 a21-a16 high address bits for dma stop address. note: a21 = 1 the stopping memory address will be in the dram. the a21 bit must be matched on the high dma start address register. 5.0 SL11R interface modes the SL11R has four modes. they are general purpose io mode, fast epp mode, 8-bit dma mode, and 8/16 dma, mailbox protocol ports mode. these modes are shared and can be configured under software control. note : the uart and 2-wire serial interface io pins are fixed in all SL11R interface modes. 5.1 general purpose io mode (gpio) in gpio mode, the SL11R has up to 32 general-purpose i/o signals available. however, there are 4 pins used by the uart and the 2-wire serial interface that cannot be used as the gpio pins. a typical application for this gpio is parallel port to usb. the SL11R executes at 48mhz -- fast enough to generate any parallel port timing. the SL11R also includes a special mode for epp timing designed for special devices that have no delay in the epp mode. other available general purpose i/o pins can be programmed for peripheral control and/or status, etc. when the SL11R interface is in gpio mode, a number of gpio pins are used to support the parallel interface. the remaining pins can be used for gpio or if desired, some can be configured for special functions. the following registers are used for all pins configured as gpio. the outputs are enabled in the i/0 control registers. note th at the output data can be read back via the output data register even if the outputs are not enabled. note : the fast dma and pwm interface will not be supported in this mode. d7 d6 d5 d4 d3 d2 d1 d0 0 0 a21 a20 a19 a18 a17 a16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 0 0 a21 a20 a19 a18 a17 a16
SL11R document #: 38-08006 rev. ** page 39 of 85 5.1.1 i/o control register 0 (0xc022: r/w) this register controls the input/output direction of the gpio data pins from gpio15 to gpio0. when any bit of this register set to one, the corresponding gpio data pin becomes an output pin. when any bit of this register is set to zero, the corresponding gpio data pin becomes an input pin. d15-0 e15-0 enable individual outputs, gpio 15-0. logic ? 1 ? enables. 5.1.2 i/o control register 1 (0xc028: r/w) this register controls the input/output direction of the gpio data pins from gpio31 to gpio16. when any bit of this register se t to one, the corresponding gpio data pin becomes an output pin. when any bit of this register is set to zero, the corresponding gpio data pin becomes an input pin. d15-0 e31-16 enable individual outputs, gpio 31-16. logic ? 1 ? enables. 5.1.3 output data register 0 (0xc01e: r/w) this register controls the output data of the gpio data pins from gpio15 to gpio0. note: a read of this register reads back the last data written, not the data on pins configured as input (see below). d15-0 o15-0 output pin data 5.1.4 output data register 1 (0xc024: r/w) this register controls the output data of the gpio data pins from gpio31 to gpio16. d15-0 o31-16 output pin data 5.1.5 input data register 0 (0xc020: read only) this register reads the input data of the gpio data pins from gpio15 to gpio0. d15-0 i15-0 input pin data 5.1.6 input data register 1 (0xc026: read only) this register reads the input data of the gpio data pins from gpio31 to gpio16. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 e15 e14 e13 e12 e11 e10 e9 e8 e7 e6 e5 e4 e3 e2 e1 e0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 e31 e30 e29 e28 e27 e26 e25 e24 e23 e22 e21 e20 e19 e18 e17 e16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 o15 o14 o13 o12 o11 o10 o9 o8 o7 o6 o5 o4 o3 o2 o1 o0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 o31 15 o30 14 o29 13 o28 12 o27 11 o26 10 o2 59 o2 48 o2 37 o2 26 o2 15 o2 04 o1 93 o1 82 o1 7 o1 60 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 i15 i14 i13 i12 i11 i10 i9 i8 i7 i6 i5 i4 i3 i2 i1 i0
SL11R document #: 38-08006 rev. ** page 40 of 85 d15-0 i31-16 input pin data figure 5-1. gpio mode block diagram\ 5.2 8/16-bit dma mode this mode includes the mailbox protocol and dma protocol . the mailbox protocol allows asynchronous exchange of data between an external processor (i.e. dsp or microprocessors) and the SL11R, via the bidirectional data port sd15-sd0 (gpio15-0). the dma protocol allows the large data blocks to be transferred to or from SL11R memory devices via the 8/16-bit dma port. the SL11R has four built-in pwm output channels available in the 8/16-bit dma mode. each channel provides a programmable timing generator sequence which can be used to interface to various line ccd, cis, cmos image sensors or can be used for other types of applications (see programmable pulse/pwm interface for more detail of controlling these pwm functions). note : any other unused io pins can be used as the gpio pins under control of the general purpose io mode (gpio). d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 i31 i30 i29 i28 i27 i26 i25 i24 i23 i22 i21 i20 i19 i18 i17 i16 internal i/o register data path enb from i/o co n t r o l r eg i s t er output data fr om output data register read back of output data register input data to input data register i/o pin
SL11R document #: 38-08006 rev. ** page 41 of 85 figure 5-2. 8/16-bit dma mode block diagram 5.2.1 mailbox protocol the physical interface for the mailbox is shared with the dma data path on the sd15-sd0 bus. when accessing the mailbox inbuff & outbuff registers, the addr pin should be driven high. the addr pin should be driven low to access the mailbox status register. the external processor and SL11R can both access the inbuff, outbuff & status mailbox registers. the SL11R includes two interrupt vectors for this mailbox protocol. whenever the external processor accesses the mailbox, the associated interrupt will be generated. note : to enable the mailbox interrupt, the bit mbx in the register 0xc00e must be enabled. the external processor cannot access the mailbox while dma is in progress. 5.2.2 inbuff data register (0xc0c4: r/w) the external processor will write to this register with the addr signal set to one and the SL11R will read this register after receiving the interrupt (if the mbx interrupt is enabled in the register 0xc00e). d15-0 d15-0 data from input mailbox 5.2.3 outbuff data register (0xc0c4: r/w) the SL11R will write to this register and the external processor will read from this register with the addr signal set to one. the SL11R will receive an interrupt after the external processor finished reading (if the mbx interrupt is enabled in the register 0xc00e). d15-0 d15-0 data for output mailbox d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 sd15-0 data15-0 inbuff outbuff status '0$exiihu ,) ,qwhuuxsw SL11R processor 2),qwhuuxsw % %* %* *+
SL11R document #: 38-08006 rev. ** page 42 of 85 5.2.4 status register (0xc0c2: read only) the external processor can read the status of the outbuff and inbuff status bits from this output buffer. the external addr pin should be driven to low when reading this status register. d1 if inbuff full d0 of outbuff full note: the SL11R also can access this register. 5.2.5 dma protocol the physical interface for the dma is shared with the mailbox protocol on the sd15-sd0 bus. if the dreq (dma request enable) bit is set, this enables SL11R dma cycles to or from the external device (scanner, printer, camera, modem or etc.). the dreq is asserted by the SL11R when data is ready to be sent or received. when the external device is ready to send data, it asserts the nwrite signal. data must be available at this point. if the external device is ready to accept data, it asserts the nread signal. the dma mode can be used to move large amounts of data to or from a variety of peripherals such as scanners, printers, cable modems, external storage devices, and others. for example for a dvc, video data from the camera can be moved via dma to an internal memory buffer for subsequent transfer to the usb host. this data can be transferred to the host via the usb dma engine (i.e. no SL11R processing is involved, since the usb has its own dma engine). users can program 8 bit or 16 bit dma transfers in either direction; peripheral to SL11R or SL11R to peripheral. a control regi ster (0xc02a) sets the dma bus width, direction and dma enable and four further registers control the dma start and end addresses (see fast dma mode, section 2.14). furthermore, if the fdma bit in register 0xc00e is enabled, an interrupt will be issued to indicate the dma operation is complete. 5.2.6 dma control register (0xc0c0: r/w) before setting this register, the low dma start address (0xc02c), high dma start address (0xc02e), the low dma stop address (0xc030) and the high dma stop address (0xc032) must be configured. d2 dreq external dreq dma enable, if set to ? 1 ? , the SL11R can dma to or from the external device (scanner or printer) by asserting the dreq signal when data is requested or ready to send. d1 d1 set to ? 1 ? d0 d0 set to ? 1 ? 5.3 fast epp mode this interface is designed to interface with a specially optimized high-speed epp interface. the SL11R processor has direct access to the epp control port. the epp function has four transfer modes: data write, data read, address write and address read. strobe signals ndtsrb and nastrb are generated by the SL11R for data or address operations respectively. the signal nwrite indicates read or write as described below. note : the fast dma and pwm interface will not be supported in this mode. any other unused io pins can be used as the gpio pins under control of thegeneral purpose io mode (gpio). d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 000000 00000000ifof d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0000000000000dreqd1d0
SL11R document #: 38-08006 rev. ** page 43 of 85 5.3.1 epp data register (0xc040: r/w) writing to this register results in the generation of a pulse on the ndtsrb output pin, with the nwrite output pin low, and the register data being driven onto the sd7-sd0 data bus. reading from this register results in the generation of a pulse on the ndtsrb output pin, with the nwrite output pin high, and data being read from the sd7-sd0 data bus. d7-d0 sd7-sd0 epp data 5.3.2 epp address register (0xc044: r/w) writing to this register results in the generation of a pulse on the nastrb output pin, with the nwrite output pin low, and the register data being driven onto the sd7-sd0 data bus. reading from this register results in the generation of a pulse on the nastrb output pin, with the nwrite output pin high, and data being read from the sd7-sd0 data bus. d7-d0 a7-a0 device and register address value from the sd7-sd0 data bus. 5.3.3 epp address buffer read register (0xc046: read only) reading this register returns existing data from read buffer to the i/o processor. the nastrb will not be asserted. d7-d0 a7-a0 read data 5.3.4 epp data buffer read register (0xc042: read only) reading this register returns existing data from read buffer to the i/o processor. the ndtsrb will not be asserted d7-d0 sd7-sd0 epp data from the sd7-sd0 data bus. 5.3.5 epp status data register (0xc04e: r/w) this register is used to read the actual status signal from gpio9-8. the p9 pin will be set to the value in d7 when written. gp io8 and gpio9 are not affected by writing to this register. d7 p9 value output on gpio21. d1 intr from the gpio8 d0 wait line from gpio9. d7 d6 d5 d4 d3 d2 d1 d0 sd7 sd6 sd5 sd4 sd3 sd2 sd1 sd0 d7 d6 d5 d4 d3 d2 d1 d0 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 sd7 sd6 sd5 sd4 sd3 sd2 sd1 sd0 d7 d6 d5 d4 d3 d2 d1 d0 p9 (gpio21) 0 0 0 0 0 intr wait
SL11R document #: 38-08006 rev. ** page 44 of 85 5.3.6 epp p_reg register (0xc050: r/w) the SL11R has a set of eight pins labeled p1-p8, which are general-purpose output pins. the functionality of each bit is select ed in the respective control register. the SL11R 16-bit processor has access to these pins through a read write, which is defined in the p_reg register. the bit assignments are noted in the following table. d7-d0 p8-p1 set to logic ? 1 ? or ? 0 ? for corresponding p output pin note: a write to this register causes the SL11R to write this out the corresponding gpio pins (except p6). the output value of the p6 will be the complement of the value written. 5.3.7 serial interface registers the SL11R supports subset of an industry standard spi serial interface, which provides the interface to serial interface device like multi-media or memory stick interface. 5.3.7.1 serial interface control & status register address c048h the serial interface port of the SL11R can be used to control certain aspects of the interface to serial memory flash devices. there are cycles (address, write or read) are implemented on this mode. d7-1 not defined. d0 b - busy. when set = '1', indicates a cycle is in progress. cleared to '0' when the cycle has completed. no new cycles are allowed until busy bit = '0'. 5.3.7.2 serial interface address register address c04ah a7-a0: address value. writing a value to this register results in an address cycle on the serial bus. the busy bit in the statu s register (c048h) goes to '1' (high) until cycle has completed. 5.3.7.3 serial interface data write register address c04ch td7-0: data to be transmitted. writing to this register initiates a write cycle on the serial data bus. the busy bit in the sta tus register (c048h) goes to '1' (high) until the cycle has completed. d7 d6 d5 d4 d3 d2 d1 d0 p8 (gpio15) p7 (gpio14) p6 (!gpio13) p5 (gpio20) p4 (gpio19) p3 (gpio18) p2 (gpio17) p1 (gpio16) d7 d6 d5 d4 d3 d2 d1 d0 0000000b d7 d6 d5 d4 d3 d2 d1 d0 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 td7 td6 td5 td4 td3 td2 td1 td0
SL11R document #: 38-08006 rev. ** page 45 of 85 5.3.7.4 serial interface data read register read onlyaddress c04ch rd7-0: read data. reading this register initiates a read cycle on the serial bus and sets the busy bit = ? 1 ? in the status register (c048h). read data is valid when the busy bit in the status register is cleared to ? 0 ? . notes: the clock rate for the serial operation is 12mhz base on the processor clock at 48mhz. to change the clock rate user can change the processor clock rate via the register c008h. a delay is needed between back to back serial accesses to allow serial shifting to occur. gpio11 will be used as the datas. gpio26 will be used as the clks. gpio25 will be used as the nens (can use this as the interrupt irq1). the register c006h need to select this mode to make the interface work. 5.4 dvc 8-bit dma mode this mode is designed to interface with ccd cameras. camera control and setup is performed through the serial control bus. the SL11R 16-bit processor has direct access to the control port and the camera operation is dependent on commands passed from the usb host to the SL11R. raw video data from the camera is input to the SL11R on the 8-bit video data bus (sd7-sd0) using a combination of clock and control signals and 8 bit dma. the signals include a clock (mck0), field index (fi), sync and blanking signals (sync, pblk), and drive signals (vd and hd). the dma engine is used to transfer the image from the 8-bit bus (sd7-sd0) to external dram port. the software uses the fast dma configuration registers. note : the pwm interface is not supported in this mode. any other unused io pins can be used as gpio pins under control of the gpio mode. 5.4.1 video status register(0xc06e: read only) the camera sends an 8 bit data bus with a number of control signals. the SL11R uses the following control signals to acquire the video data: mck0 from camera pixel clock = 9.534965mhz fi from camera field index. contains 1 vertical sweep + blank vd from camera active during vertical sweep. pblk from camera active during horizontal sweep. sd7-sd0 from camera ccd video data. n_rst to camera active low reset the first 8 bytes of data is discarded from the video stream starting at the assertion of each pblk. after pblk is de-asserted, 7 more bytes of data are taken. the video control and status register allows the acquisition of video images and provides power and reset controls for the camera. d7-5 reserved always = '0' d4 vrst video reset. '0' resets camera (see note). d3 p-cont when set = '1' powers up camera. d2 reserved always = '0'. d7 d6 d5 d4 d3 d2 d1 d0 rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 vrst p-cont 0 f sc
SL11R document #: 38-08006 rev. ** page 46 of 85 d1 f when set = ? 1 ? capture even then odd field else when ? 0 ? capture even field only. d0 sc start capture when set = ? 1 ? , clears to ? 0 ? when done. note: after p-cont is set high to provide camera power, the video reset must be held low a minimum of 100 milliseconds. 5.4.2 camera serial interface registers the serial interface port of the SL11R is used to pass control information to the camera and to communicate with serial eprom1, and eprom2 (eprom 1 is used to store camera default data). the serial port control register determines if the next operation will be a write cycle to the camera or the eeprom, or if the operation will be a read cycle of the eprom. when an eprom or camera cycle is required the device must be selected in the control register, and an eeprom address location must be written to the serial interface address register. when a read cycle is selected, writing the busy bit begins the cycle, and when completed, the valid returned data can be read in the serial interface data read register. the SL11R has a dedicated serial bus to support the camera and eprom. on power up, an SL11R signal, aeep, is driven high, (aeep connects to the camera dsp device), the SL11R camera serial bus is three-stated, which allows the camera dsp to read the camera default data directly from the eeprom. (during this time the dsp drives the serial clock to the eeprom and the ccs select line to the SL11R, eep1 is driven high from the SL11R). after a timed interval, the aeep line is driven low and the SL11R can now communicate to the camera via the camera serial port. 5.4.3 serial interface control & status register (0xc068: r/w) d7-3 reserved 0 d2-d1 m1-m0 mode setting: 11 = aeep mode 10 = eprom 2 01 = eprom1 00 = dsp processor d0 busy when set = ? 1 ? , initiates a cycle to selected target. cleared to ? 0 ? when the cycle has completed. no new cycles are allowed until busy bit = ? 0 ? . 5.4.4 serial interface address register (0xc06a: write only) d8-6 p2- p0 command: 101 = write, 110 = read d5-0 a5-a0 eeprom or camera register address. 5.4.5 serial interface data write register (0xc06c: write only) when data is transmitted, setting the busy bit in the control status register initiates transmission. d15-0 t15-0 data to be transmitted. d7 d6 d5 d4 d3 d2 d1 d0 00000m1m0busy d8 d7 d6 d5 d4 d3 d2 d1 d0 p2 p1 p0 a5 a4 a3 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 t15 t14 t13 t12 t11 t10 t9 t8 t7 t6 t5 t4 t3 t2 t1 t0
SL11R document #: 38-08006 rev. ** page 47 of 85 5.4.6 serial interface data read register (0xc06c: read only) read cycle data from the selected device in control status register, and address specified in the address register. data is val id after a read cycle has been initiated by setting the busy bit in the status register. data is valid after busy bit clears to ? 0 ? . d15-0 r15-0 read data from the sd7-sd0 data bus. 5.4.7 i/o address map d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 i/o address map function address mode usb endpoint 0 address register 0x0120 r/w usb endpoint 0 count register 0x0122 r/w usb endpoint 1 address register 0x0124 r/w usb endpoint 1 count register 0x0126 r/w usb endpoint 2 address register 0x0128 r/w usb endpoint 2 count register 0x012a r/w usb endpoint 3 address register 0x012c r/w usb endpoint 3 count register 0x012e r/w configuration register 0xc006 r/w speed control register 0xc008 r/w power down control register 0xc00a r/w watchdog timer count & control register 0xc00c r/w interrupt enable register 0xc00e r/w timer 0 count register 0xc010 r/w timer 1 count register 0xc012 r/w breakpoint register 0xc014 r/w extended page 1 map register 0xc018 r/w extended page 2 map register 0xc01a r/w gpio interrupt control register 0xc01c r/w output data register 0 0xc01e r/w input data register 0 0xc020 read only i/o control register 0 0xc022 r/w output data register 1 0xc024 r/w input data register 1 0xc026 read only i/o control register 1 0xc028 r/w dma control register 0xc02a r/w low dma start address register 0xc02c r/w high dma start address register 0xc02e r/w
SL11R document #: 38-08006 rev. ** page 48 of 85 low dma stop address register 0xc030 r/w high dma stop address register 0xc032 r/w dram control register 0xc038 r/w extended memory control register 0xc03a r/w memory control register 0xc03e r/w epp data register 0xc040 r/w epp data buffer read register 0xc042 read only epp address register 0xc044 r/w epp address buffer read register 0xc046 read only epp status data register 0xc04e r/w epp p_reg register 0xc050 r/w serial interface control & status register 0xc068 r/w serial interface address register 0xc06a write only serial interface data write register 0xc06c write only serial interface data read register 0xc06c read only video status register 0xc06e read only usb global control & status register 0xc080 r/w usb frame number register 0xc082 read only usb address register 0xc084 r/w usb command done register 0xc086 write only usb endpoint 0 control & status register 0xc090 r/w usb endpoint 1 control & status register 0xc092 r/w usb endpoint 2 control & status register 0xc094 r/w usb endpoint 3 control & status register 0xc096 r/w dma control register 0xc0c0 r/w status register 0xc0c2 read only inbuff data register 0xc0c4 r/w outbuff data register 0xc0c4 r/w uart control register 0xc0e0 r/w uart status register 0xc0e2 read only uart transmit data register 0xc0e4 write only uart receive data register 0xc0e4 read only pwm control register 0xc0e6 r/w pwm maximum count register 0xc0e8 r/w pwm channel 0 start register 0xc0ea r/w pwm channel 0 stop register 0xc0ec r/w i/o address map (continued) function address mode
SL11R document #: 38-08006 rev. ** page 49 of 85 6.0 physical connection 6.1 package type 100 pqfp. 6.2 gpio and 8/16-bit dma modes ? pin assignment and description pwm channel 1 start register 0xc0ee r/w pwm channel 1 stop register 0xc0f0 r/w pwm channel 2 start register 0xc0f2 r/w pwm channel 2 stop register 0xc0f4 r/w pwm channel 3 start register 0xc0f6 r/w pwm channel 3 stop register 0xc0f8 r/w pwm cycle count register 0xc0fa r/w gpio and 8/16-bit dma modes ? pin assignment and description pin name pin no. gpio pins pin type gpio & 8/16-bit dma modes pin chip revision 1.1 vdd 1 power +3.3 vdc supply d0 2 bidir external memory data bus, data0 d1 3 bidir external memory data bus, data1 d2 4 bidir external memory data bus, data2 d3 5 bidir external memory data bus, data3 d4 6 bidir external memory data bus, data4 d5 7 bidir external memory data bus, data5 d6 8 bidir external memory data bus, data6 d7 9 bidir external memory data bus, data7 d8 10 bidir external memory data bus, data8 d9 11 bidir external memory data bus, data9 d10 12 bidir external memory data bus, data10 d11 13 bidir external memory data bus, data11 gnd 14 gnd digital ground. x1 15 input external 48-mhz crystal or clock input. x2 16 output external crystal output. no connection when x1 is used for clock input vdd 17 power +3.3 vdc supply d12 18 bidir external memory data bus, data12 d13 19 bidir external memory data bus, data13 d14 20 bidir external memory data bus, data14 d15 21 bidir external memory data bus, data15 a20 22 output external memory address bus, a20 a19 23 output external memory address bus, a19 a18 24 output external memory address bus, a18 i/o address map (continued) function address mode
SL11R document #: 38-08006 rev. ** page 50 of 85 a17 25 output external memory address bus, a17 a16 26 output external memory address bus, a16 a15 27 output external memory address bus, a15 a14 28 output external memory address bus, a14 a13 29 output external memory address bus, a13 a12 30 output external memory address bus, a12 a11 31 output external memory address bus, a11 a10 32 output external memory address bus, a10 a9 33 output external memory address bus, a9 a8 34 output external memory address bus, a8 a7 35 output external memory address bus, a7 a6 36 output external memory address bus, a6 a5 37 output external memory address bus, a5 a4 38 output external memory address bus, a4 a3 39 output external memory address bus, a3 gnd 40 gnd digital ground. a2 41 output external memory address bus, a2 a1 42 output external memory address bus, a1 a0 43 output external memory address bus, a0 test 44 input no connection, mfg test only note: SL11Rb nc=48 mhz, gnd=12 mhz nwrl 45 output active low, write to lower bank of external sram nwrh 46 output active low, write to upper bank of external sram nrd 47 output active low, read from external sram or rom nreset 48 input master reset. SL11R device active low reset input. nras 49 output active low, dram row address select vdd 50 power +3.3 vdc supply vdd 51 power +3.3 vdc supply ncasl 52 output active low, dram column low address select ncash 53 output active low, dram column high address select ndramoe 54 output active low, dram output enable ndramwr 55 output active low, dram write nxramsel 56 output active low, select external sram (16 bit) nxromsel 57 output active low, select external rom nxmemsel 58 output active low, select external memory bus, external sram, dram, rom or any memory mapped device x_pclk 59 bidir see register 0xc006 for more information seclk 60 gpio31 bidir seclk, serial eeprom clock, or gpio31 sedo 61 gpio30 bidir sedo, serial flash eprom data, or gpio30 this pin requires a 5-k ? pull-up. usb_pu 62 gpio29 bidir turn on/off d+ pull up resistor, or gpio29 uart_txd 63 gpio28 output uart transmit data (out), or gpio28 gpio and 8/16-bit dma modes ? pin assignment and description (continued) pin name pin no. gpio pins pin type gpio & 8/16-bit dma modes pin chip revision 1.1
SL11R document #: 38-08006 rev. ** page 51 of 85 gnd 64 gnd digital ground. gnd 65 gnd digital ground. uart_rxd 66 gpio27 input uart receive data (in), or gpio27 pwr_off 67 gpio26 bidir this signal can be used for device low-power mode, it will turn off or disable external powers to the peripheral in suspend mode. once usb power is resumed, external power can be enabled again irq1 (in) 68 gpio25 bidir gpio25, or irq1 (in) interrupts the SL11R processor pwm3, or irq0 (in) 69 gpio24 bidir irq0 (in) interrupts the SL11R processor or pwm. see the pwm control register set-up for more information pwm2 70 gpio23 bidir same as above or gpio23 pwm1 71 gpio22 bidir same as above or gpio22 pwm0 72 gpio21 bidir same as above or gpio21 dreq 73 gpio20 bidir dma request enable. dreq indicates that SL11R is ready to accept or send data from/to an external device. dreq along with ncs, nwrite and nread bits are the dma handshake signals for the main sdata port, or gpio20. addr 74 gpio19 bidir addr =1, read/write data from the inbuf/outbuff, addr=0 read data from the status register, or gpio19 vdd 75 power +3.3 vdc supply ncs 76 gpio18 bidir cs (in) active low, selects the bidirectional sdata port, or gpio18 nwrite 77 gpio17 bidir active input low signal used to indicate write data transfers to the general bidirectional sd15-0 data port. signal is driven high for read transfers to the SL11R, or gpio17 nread 78 gpio16 bidir active low input signal used to indicate read data transfers from the general bidirectional sd15-0 data port. or gpio16 gnd 79 gnd digital ground. sd15 80 gpio15 bidir main bidirectional sdata port bit 15, or gpio15 sd14 81 gpio14 bidir main bidirectional sdata port bit 14, or gpio14 sd13 82 gpio13 bidir main bidirectional sdata port bit 13, or gpio13 sd12 83 gpio12 bidir main bidirectional sdata port bit 12, or gpio12 sd11 84 gpio11 bidir main bidirectional sdata port bit 11, or gpio11 sd10 85 gpio10 bidir main bidirectional sdata port bit 10, or gpio10 sd9 86 gpio9 bidir main bidirectional sdata port bit 9, or gpio9 vdd1 87 power usb +3.3 vdc supply. data+ 88 bidir usb differential data signal high side. data- 89 bidir usb differential data signal low side. gnd1 90 gnd usb digital ground. sd8 91 gpio8 bidir main bidirectional sdata port bit 8, or gpio8 sd7 92 gpio7 bidir main bidirectional sdata port bit 7, or gpio7 sd6 93 gpio6 bidir main bidirectional sdata port bit 6, or gpio6 sd5 94 gpio5 bidir main bidirectional sdata port bit 5, or gpio5 sd4 95 gpio4 bidir main bidirectional sdata port bit 4, or gpio4 sd3 96 gpio3 bidir main bidirectional sdata port bit 3, or gpio3 sd2 97 gpio2 bidir main bidirectional sdata port bit 2, or gpio2 sd1 98 gpio1 bidir main bidirectional sdata port bit 1, or gpio1 gpio and 8/16-bit dma modes ? pin assignment and description (continued) pin name pin no. gpio pins pin type gpio & 8/16-bit dma modes pin chip revision 1.1
SL11R document #: 38-08006 rev. ** page 52 of 85 6.3 fast epp pin assignment and description sd0 99 gpio0 bidir main bidirectional sdata port bit 0, or gpio0 vdd 100 power +3.3 vdc supply fast epp pin assignment and description pin name pin no. gpio pins pin type gpio & fast epp pin chip revision 1.1 vdd 1 power +3.3 vdc supply d0 2 bidir external memory data bus, data0 d1 3 bidir external memory data bus, data1 d2 4 bidir external memory data bus, data2 d3 5 bidir external memory data bus, data3 d4 6 bidir external memory data bus, data4 d5 7 bidir external memory data bus, data5 d6 8 bidir external memory data bus, data6 d7 9 bidir external memory data bus, data7 d8 10 bidir external memory data bus, data8 d9 11 bidir external memory data bus, data9 d10 12 bidir external memory data bus, data10 d11 13 bidir external memory data bus, data11 gnd 14 gnd digital ground. x1 15 input external 48-mhz crystal or clock input. x2 16 output external crystal output. no connection when x1 is used for clock input vdd 17 power +3.3 vdc supply d12 18 bidir external memory data bus, data12 d13 19 bidir external memory data bus, data13 d14 20 bidir external memory data bus, data14 d15 21 bidir external memory data bus, data15 a20 22 output external memory address bus, a20 a19 23 output external memory address bus, a19 a18 24 output external memory address bus, a18 a17 25 output external memory address bus, a17 a16 26 output external memory address bus, a16 a15 27 output external memory address bus, a15 a14 28 output external memory address bus, a14 a13 29 output external memory address bus, a13 a12 30 output external memory address bus, a12 a11 31 output external memory address bus, a11 a10 32 output external memory address bus, a10 a9 33 output external memory address bus, a9 a8 34 output external memory address bus, a8 a7 35 output external memory address bus, a7 gpio and 8/16-bit dma modes ? pin assignment and description (continued) pin name pin no. gpio pins pin type gpio & 8/16-bit dma modes pin chip revision 1.1
SL11R document #: 38-08006 rev. ** page 53 of 85 a6 36 output external memory address bus, a6 a5 37 output external memory address bus, a5 a4 38 output external memory address bus, a4 a3 39 output external memory address bus, a3 gnd 40 gnd digital ground. a2 41 output external memory address bus, a2 a1 42 output external memory address bus, a1 a0 43 output external memory address bus, a0 test 44 input no connection, mfg test only nwrl 45 output active low, write to lower bank of external sram nwrh 46 output active low, write to upper bank of external sram nrd 47 output active low, read from external sram or rom nreset 48 input master reset. SL11R device active low reset input. nras 49 output active low, dram row address select vdd 50 power +3.3 vdc supply vdd 51 power +3.3 vdc supply ncasl 52 output active low, dram column low address select ncash 53 output active low, dram column high address select ndramoe 54 output active low, dram output enable ndramwr 55 output active low, dram write nxramsel 56 output active low, select external sram (16 bit) nxromsel 57 output active low, select external rom nxmemsel 58 output active low, select external memory bus, external sram, dram, rom or any memory mapped device x_pclk 59 bidir see register 0xc006 for more information seclk 60 gpio31 bidir seclk, serial eeprom clock, or gpio31 sedo 61 gpio30 bidir sedo, serial flash eprom data, or gpio30 this pin requires a 5k ohm pull-up. gpio29 62 gpio29 bidir gpio29 uart_txd 63 gpio28 output uart transmit data (out), or gpio28 gnd 64 gnd digital ground. gnd 65 gnd digital ground. uart_rxd 66 gpio27 input uart receive data (in), or gpio27 nens 67 gpio26 output serial eprom control signal clks 68 gpio25 output serial eprom clock ndtsrb 69 gpio24 output epp data strobe nastrb 70 gpio23 output epp address strobe nwrite 71 gpio22 output epp write strobe p9 72 gpio21 output p register p5 73 gpio20 output p register or pwr_off p4 74 gpio19 output p register fast epp pin assignment and description (continued) pin name pin no. gpio pins pin type gpio & fast epp pin chip revision 1.1
SL11R document #: 38-08006 rev. ** page 54 of 85 6.4 dvc 8-bit dma mode pin assignment and description vdd 75 power +3.3 vdc supply p3 76 gpio18 output p register or usb_pu (usb data+ pull up) p2 77 gpio17 output p register p1 78 gpio16 output p register gnd 79 gnd digital ground. p6 80 gpio15 output p register p7 81 gpio14 output p register p8 82 gpio13 output p register gpio12 83 gpio12 bidir gpio12 datas 84 gpio11 bidir data strobe for serial eprom vreq 85 gpio10 input tbd wait 86 gpio9 bidir epp wait signal vdd1 87 power usb +3.3 vdc supply. data+ 88 bidir usb differential data signal high side. data- 89 bidir usb differential data signal low side. gnd1 90 gnd usb digital ground. intr 91 gpio8 input epp intr pin sd7 92 gpio7 bidir epp data bit 7 sd6 93 gpio6 bidir epp data bit 6 sd5 94 gpio5 bidir epp data bit 5 sd4 95 gpio4 bidir epp data bit 4 sd3 96 gpio3 bidir epp data bit 3 sd2 97 gpio2 bidir epp data bit 2 sd1 98 gpio1 bidir epp data bit 1 sd0 99 gpio0 bidir epp data bit 0 vdd 100 power +3.3 vdc supply dvc 8-bit dma mode pin assignment and description pin name pin no. gpio pins pin type gpio & dvc 8-bit dma modes pin chip revision 1.1 vdd 1 power +3.3 vdc supply d0 2 bidir external memory data bus, data0 d1 3 bidir external memory data bus, data1 d2 4 bidir external memory data bus, data2 d3 5 bidir external memory data bus, data3 d4 6 bidir external memory data bus, data4 d5 7 bidir external memory data bus, data5 d6 8 bidir external memory data bus, data6 d7 9 bidir external memory data bus, data7 d8 10 bidir external memory data bus, data8 fast epp pin assignment and description (continued) pin name pin no. gpio pins pin type gpio & fast epp pin chip revision 1.1
SL11R document #: 38-08006 rev. ** page 55 of 85 d9 11 bidir external memory data bus, data9 d10 12 bidir external memory data bus, data10 d11 13 bidir external memory data bus, data11 gnd 14 gnd digital ground. x1 15 input external 48-mhz crystal or clock input. x2 16 output external crystal output. no connection when x1 is used for clock input vdd 17 power +3.3 vdc supply d12 18 bidir external memory data bus, data12 d13 19 bidir external memory data bus, data13 d14 20 bidir external memory data bus, data14 d15 21 bidir external memory data bus, data15 a20 22 output external memory address bus, a20 a19 23 output external memory address bus, a19 a18 24 output external memory address bus, a18 a17 25 output external memory address bus, a17 a16 26 output external memory address bus, a16 a15 27 output external memory address bus, a15 a14 28 output external memory address bus, a14 a13 29 output external memory address bus, a13 a12 30 output external memory address bus, a12 a11 31 output external memory address bus, a11 a10 32 output external memory address bus, a10 a9 33 output external memory address bus, a9 a8 34 output external memory address bus, a8 a7 35 output external memory address bus, a7 a6 36 output external memory address bus, a6 a5 37 output external memory address bus, a5 a4 38 output external memory address bus, a4 a3 39 output external memory address bus, a3 gnd 40 gnd digital ground. a2 41 output external memory address bus, a2 a1 42 output external memory address bus, a1 a0 43 output external memory address bus, a0 test 44 input no connection, mfg test only nwrl 45 output active low, write to lower bank of external sram nwrh 46 output active low, write to upper bank of external sram nrd 47 output active low, read from external sram or rom nreset 48 input master reset. SL11R device active low reset input. nras 49 output active low, dram row address select vdd 50 power +3.3 vdc supply vdd 51 power +3.3 vdc supply dvc 8-bit dma mode pin assignment and description (continued) pin name pin no. gpio pins pin type gpio & dvc 8-bit dma modes pin chip revision 1.1
SL11R document #: 38-08006 rev. ** page 56 of 85 ncasl 52 output active low, dram column low address select ncash 53 output active low, dram column high address select ndramoe 54 output active low, dram output enable ndramwr 55 output active low, dram write nxramsel 56 output active low, select external sram (16 bit) nxromsel 57 output active low, select external rom nxmemsel 58 output active low, select external memory bus, external sram, dram, rom or any memory mapped device x_pclk 59 bidir see register 0xc006 for more information seclk 60 gpio31 bidir seclk, serial eeprom clock, or gpio31 sedo 61 gpio30 bidir sedo, serial flash eprom data, or gpio30 this pin requires a 5k ohm pull-up. gpio29 62 gpio29 bidir gpio29 uart_txd 63 gpio28 output uart transmit data (out), or gpio28 gnd 64 gnd digital ground. gnd 65 gnd digital ground. uart_rxd 66 gpio27 input uart receive data (in), or gpio27 gpio26 67 gpio26 bidir gpio26 irq1 (in) 68 gpio25 bidir gpio25, or irq1 (in) interrupts the SL11R processor irq0 (in) 69 gpio24 bidir irq0 (in) interrupts the SL11R processor or gpio24 gpio23 70 gpio23 bidir gpio23 gpio22 71 gpio22 bidir gpio22 nvid_rst 72 gpio21 output video reset pin p_cont 73 gpio20 output p_cont pin agc_c 74 gpio19 output agc_c control pin vdd 75 power +3.3 vdc supply aeep 76 gpio18 output aepp pin dsp_cs 77 gpio17 output dsp chip select pin eep2_cs 78 gpio16 bidir serial eprom2 chip select gnd 79 gnd digital ground. eep1_cs 80 gpio15 output serial eprom1 chip select do 81 gpio14 output serial eprom data out pin sk 82 gpio13 input serial eprom clock pin pblk 83 gpio12 input pblk from ccd vd 84 gpio11 input vd from ccd fi 85 gpio10 input fi from ccd mck0 86 gpio9 bidir mck0 from ccd vdd1 87 power usb +3.3 vdc supply. data+ 88 bidir usb differential data signal high side. data- 89 bidir usb differential data signal low side. gnd1 90 gnd usb digital ground. dvc 8-bit dma mode pin assignment and description (continued) pin name pin no. gpio pins pin type gpio & dvc 8-bit dma modes pin chip revision 1.1
SL11R document #: 38-08006 rev. ** page 57 of 85 7.0 SL11R cpu programming guide this is the preliminary specification for the SL11R processor instruction set. 7.1 instruction set overview this document describes the SL11R cpu instruction set, registers and addressing modes, instruction format, etc. the SL11R processor uses a unified program and data memory space; although this ram is also integrated into the SL11R core, provision has been made for external memory as well. the SL11R processor engine incorporates 38 registers: fifteen general-purpose registers, a stack pointer, sixteen registers mapped into ram, a program counter, and a regbank register whose function will be described in a subsequent section. the SL11R processor engine supports byte and word addressing. subsequent sections of this document will describe: the SL11R processor engine (qt engine) register set SL11R processor engine instruction format SL11R processor engine addressing modes SL11R processor engine instruction set 7.2 reset vector on receiving hardware reset, the SL11R processor jumps to address 0xfff0, which is an internal rom address. 7.3 register set the SL11R processor incorporates 16-bit general-purpose registers called r0..r15, a regbank register, and a program counter, along with various other registers. the function of each register is defined as follows: 7.4 general-purpose registers the general-purpose registers can be used to store intermediate results, and to pass parameters to and return them from subroutine calls. di 91 gpio8 bidir serial eprom data input sd7 92 gpio7 input sdata port bit 7, or gpio7 sd6 93 gpio6 input sdata port bit 6, or gpio6 sd5 94 gpio5 input sdata port bit 5, or gpio5 sd4 95 gpio4 input sdata port bit 4, or gpio4 sd3 96 gpio3 input sdata port bit 3, or gpio3 sd2 97 gpio2 input sdata port bit 2, or gpio2 sd1 98 gpio1 input sdata port bit 1, or gpio1 sd0 99 gpio0 input sdata port bit 0, or gpio0 vdd 100 power +3.3 vdc supply name function r0-r14 general purpose registers r15 stack pointer pc program counter regbank forms base address for registers r0-r15 flags contains flags: defined below interrupt enable bit masks to enable/disable various interrupts dvc 8-bit dma mode pin assignment and description (continued) pin name pin no. gpio pins pin type gpio & dvc 8-bit dma modes pin chip revision 1.1
SL11R document #: 38-08006 rev. ** page 58 of 85 7.5 general purpose/address registers in addition to acting as general-purpose registers, registers r8-r14 can also serve as pointer registers. instructions can acce ss ram locations by referring to any of these registers. in normal operation, register r15 is reserved for use as a stack pointer. 7.6 regbank register (0xc002: r/w) registers r0..r15 are mapped into ram via the regbank register. the regbank register is loaded with a base address, of which the 11 most significant bits are used. a read from or write to one of the registers will generate a ram address by: shifting the 4 least significant bits of the register number left by 1. or-ing the shifted bits of the register number with the upper 11 bits of the regbank register. forcing the least significant bit to 0. for example, if the regbank register is left at its default value of 100 hex, a read of register r14 would read address 11c hex . note: regardless of the value loaded into the regbank register, bits 0..4 will be ignored. 7.7 flags register (0xc000: read only) the SL11R processor uses these flags: z zero : instruction execution resulted in a result of 0 c carry/borrow : arithmetic instruction resulted in a carry (for addition) or a borrow (for subtraction) o overflow : arithmetic result was either larger than the destination operand size (for addition) or smaller than the destination operand should allow for subtraction ssign : set if ms result bit is ? 1 ? i global interrupts enabled if ? 1 ? note: flag behavior for each instruction will be described in the following section 7.8 instruction format to understand addressing modes supported by the SL11R processor, you must know how the instruction format is defined. in general, the instructions include four bits for the instruction opcode , six bits for the source operand, and six bits for the destination operand. some instructions, especially single operand-operator and program control instructions, will not adhere strictly to this format . they will be discussed in detail in turn. register hex value binary value regbank 0100 00000001000 xxxxx r14 000e << 1 = 001c xxxxxxxxxx 011100 ram location 011c 0000000100011100 flag bit: 1514131211109876543210 0000 0000000 isocz add bit: 1514131211109876543210 opcode source destination
SL11R document #: 38-08006 rev. ** page 59 of 85 7.9 addressing modes this section describes in detail the six-operand field bits referred to in the previous section as source and destination . bear in mind that although the discussion refers to bits 0 through 5, the same bit definitions apply to the ? source ? operand field, bits 6 through 11. these are the basic addressing modes in the SL11R processor. notes: b/w: ? 1 ? for byte-wide access, ? 0 ? for word access. indirect with auto increment and byte-wide indirect addressing is illegal with the stack pointer (r15). 7.10 register addressing in register addressing, any one of registers r0-r15 can be selected using bits 0-3. if register addressing is used, operands ar e always 16-bit operands, since all registers are 16-bit registers. for example, an instruction using register r7 as an operand w ould fill the operand field like this: 7.11 immediate addressing in immediate addressing, the instruction word is immediately followed by the source operand. for example, the operand field would be filled with: note: in immediate addressing, the source operand must be 16 bits wide, eliminating the need for a b/w bit. 7.12 direct addressing in direct addressing, the word following the instruction word is used as an address into ram. again, the operand can be either byte or word sized, depending on the state of bit 3 of the operand field. for example, to do a word-wide read from a direct add ress, the source operand field would be formed like this: note: for a memory-to-memory move, the instruction word would be followed by two words, the first being the source address and the second being the destination . 7.13 indirect addressing indirect addressing is accomplished using address registers r8-15. in indirect addressing, the operand is found at the memory address pointed to by the register. since only eight address registers exist, only three bits are required to select an address register. for example, register r10 (binary 1010) can be selected by ignoring bit 3, leaving the bits 010. bit 3 of the operand field mode 54 3 210 register 0 0 r r r r immediate 0 1 1 1 1 1 direct 10b/w111 indirect 01b/wrrr indirect with auto increment 1 0 b/w r r r indirect with index 1 1 b/w r r r bits 54321 0 register operand 00011 1 bits 54321 0 operand field 01111 1 bits 54321 0 i/o operand 10011 1
SL11R document #: 38-08006 rev. ** page 60 of 85 is then used as the byte/word bit, set to ? 0 ? to select word or ? 1 ? to select byte addressing. in this example, a byte-wide operand is selected at the memory location pointed to by register r10: note: for register r15, byte-wide operands are prohibited. if bit 3 is set high, the instruction is decoded differently, as explained at the top of this section. 7.14 indirect addressing with auto increment indirect addressing with auto increment works identically to indirect addressing, except that at the end of the read or write c ycle, the register is incremented by 1 or 2 (depending whether it is a byte-wide or word-wide access.) this mode is prohibited for register r15. if bits 0..2 are all high, the instruction is decoded differently, as explained at th e top of this section. 7.15 indirect addressing with offset in indirect addressing with offset, the instruction word is followed by a 16-bit word that is added to the contents of the addr ess register to form the address for the operand. the offset is an unsigned 16-bit word, and will ? wrap ? to low memory addresses if the register and offset add up to a value greater than the size of the processor ? s address space. 7.16 stack pointer (r15) special handling register r15 is designated as the stack pointer, and has these special behaviors: if addressed in indirect mode, the register pre-decrements on a write instruction, and post-increments on a read instruction, emulating push and pop instructions. byte-wide reads or writes are prohibited in indirect mode. if r15 is addressed in indirect with index mode, it does not auto-increment or auto-decrement. SL11R - cpu instruction set the instruction set can be roughly divided into three classes of instructions: dual operand instructions (instructions with two operands, a source and a destination) program control instructions (jump, call and return) single operand instructions (instructions with only one operand: a destination) 7.17 dual operand instructions instructions with source and destination, for all dual operand instructions, byte values are zero extended by default. destination:= source flags affected: none destination:= destination + source flags affected: z, c, o, s bits 54321 0 memory operand 01101 0 mov bit: 1514131211109876543210 0000 source destination add bit: 1514131211109876543210 0001 source destination
SL11R document #: 38-08006 rev. ** page 61 of 85 destination:= destination + source + carry bit flags affected: z, c, o, s destination:= destination - source flags affected: z, c, o, s destination:= destination - source - carry bit flags affected: z, c, o, s [not saved] = destination - source flags affected: z, c, o, s destination:= destination & source flags affected: z, s [not saved]:= destination & source flags affected: z, s destination:= destination | source flags affected: z, s addc bit: 1514131211109876543210 0010 source destination sub bit: 1514131211109876543210 0011 source destination subb bit: 1514131211109876543210 0100 source destination cmp bit: 1514131211109876543210 0101 source destination and bit: 1514131211109876543210 0110 source destination test bit: 1514131211109876543210 0111 source destination or bit: 1514131211109876543210 1000 source destination
SL11R document #: 38-08006 rev. ** page 62 of 85 destination:= destination ^ source flags affected: z, s 7.18 program control instructions pc:= pc + (offset*2)(offset is a 7-bit signed number from -64..+63) pc:= [destination](destination is computed in the normal fashion for operand fields) pc:= [r15] r15++ r15-- [r15]:= pc pc = [destination] [r15]:= pc r15-- pc = [int vector * 2] this instruction allows the programmer to implement software interrupts. int vector is multiplied by two, and zero extended to 16 bits. note: interrupt vectors 0 through 31 may be reserved for hardware interrupts, depending on the application. the condition (cccc) bits for all of the above instructions are defined as: xor bit: 1514131211109876543210 1001 source destination jcc jump relative cccc bit: 151413121110987 6 543210 1100 cccc 0 offset jccl jump absolute cccc bit: 1514131211109876 543210 1100 cccc 1 0 destination rcc ret cccc bit: 1514131211109876 543210 1100 cccc 1 0 010111 ccc call cccc bit: 1514131211109876 543210 1010 cccc 1 0 destination int bit: 151413121110987 6 543210 1010 0000 0 int vector
SL11R document #: 38-08006 rev. ** page 63 of 85 note: for the jump mnemonics, adding an ? l ? to the end indicates a long or absolute jump. adding an ? s ? to the end indicates a short or relative jump. if nothing is added, the assembler will choose ? s ? or ? l. ? 7.19 single operand operation instructions since single operand instructions do not require a source field, the format of the single operand operation instructions is sli ghtly different. notice that the opcode field is expanded to seven bits wide. the four most significant bits for all instructions of this class are ? 1101. ? in addition, there is space for an optional three bit immediate value, which is used in a manner appropriate to the instruction . the destination field functions exactly as it does in the dual operand operation instructions. note: for the shr, shl, ror, rol, addi and subi instructions, the three-bit count or n operand is incremented by 1 before it is used. the SL11R qt assembler takes this into account. destination:= destination >> count flags affected: z, c, s note: the shr instruction shifts in sign bits. the c flag is set with last bit shifted out of lsb. condition cccc bits description jump mnemonic call mnemonic ret mnemonic z 0000 z=1 jz cz rz nz 0001 z=0 jnz cnz rnz c / b 0010 c=1 jc cc rc nc / ae 0011 c=0 jnc rnc rnc s 0100 s=1 js cs rs ns 0101 s=0 jns cns rns o 0110 o=1 jo co ro no 0111 o=0 jno cno rno a / nbe 1000 (z=0 and c=0) ja ca ra be / na 1001 (z=1 or c=1) jbe cbe rbe g / nle 1010 (o= s and z=0) jg cg rg ge / nl 1011 (o=s) jge cge rge l / nge 1100 (o s) jl cl rl le / ng 1101 (o s or z=1) jle cle rle (not used) 1110 unconditional 1111 unconditional jmp call ret instruction bit: 15141312 11 1098 7 6543210 1101*** [param] destination shr bit: 1514131211109876543210 1101000 count-1 destination
SL11R document #: 38-08006 rev. ** page 64 of 85 destination:= destination << count flags affected: z, c, s note : the c flag is set with last bit shifted out of msb. works identically to the shr instruction, except that the lsb of destination is rotated into the msb, as opposed to shr, which discards that bit flags affected: z, c, s works identically to the shl instruction, except that the msb of destination is rotated into the lsb, as opposed to shl, which discards that bit flags affected: z, c, s destination:= destination + n flags affected: z, s destination:= destination - n flags affected: z, s destination:= ~destination (bitwise 1 ? s complement negation) flags affected: z, s destination:= -destination (2 ? s complement negation) flags affected: z, o, c, s shl bit: 1514131211109876543210 1101001 count-1 destination ror bit: 1514131211109876543210 1101010 count-1 destination rol bit: 1514131211109876543210 1101011 count-1 destination addi bit: 1514131211109876543210 1101100 n-1 destination subi bit: 1514131211109876543210 1101101 n-1 destination not bit: 1514131211109876543210 1101111 000 destination neg bit: 1514131211109876543210 1101111 001 destination
SL11R document #: 38-08006 rev. ** page 65 of 85 sign-extends a byte in the lower eight bits of [destination] to a 16-bit signed word (integer). flags affected: z, s 7.20 miscellaneous instructions sets interrupt enable flag flags affected: i note : the sti instruction takes effect 1 cycle after it is executed. clears interrupt enable flag flags affected: i set carry bit. flags affected: c clear carry bit. flags affected: c 7.21 built-in macros for the programmer ? s convenience, the SL11R qt assembler implements several built-in macros. the table below shows the macros, and the mnemonics for the code that the assembler will generate for these macros. cbw bit: 1514131211109876543210 1101111 010 destination sti bit: 1514131211109876543210 1101111 111 000000 cli bit: 1514131211109876543210 1101111 111 000001 stc bit: 1514131211109876543210 1101111 111 000010 clc bit: 1514131211109876543210 1101111 111 000011 macro assembler will generate inc x addi x, 1 dec x subi x, 1 push x mov [r15], x pop x mov x, [r15]
SL11R document #: 38-08006 rev. ** page 66 of 85 7.22 SL11R processor instruction set summary notes: 10. the number in the ? clock cycles ? column reflects the number of clock cycles for register or immediate accesses. for each occurrence of other types of accesses, include the appropriate ? clock adder ? as listed in the addressing modes table below. 11. all clock cycle values assume zero wait-states. 12. a shift of one is done in four clock cycles, each additional shift adds two more clock cycles. mnemonic operands description opcode flags affected clock cycles notes msb lsb mov s,d move s to d 0000 ssss ssdd dddd none 5 10,11 add s,d add s to d 0001 ssss ssdd dddd z,c,o,s 5 10,11 addc s,d add s to d with carry 0010 ssss ssdd dddd z,c,o,s 5 10,11 sub s,d subtract s from d 0011 ssss ssdd dddd z,c,o,s 5 10,11 subb s,d subtract s from d with carry 0100 ssss ssdd dddd z,c,o,s 5 10,11 cmp s,d compare d with s 0101 ssss ssdd dddd z,c,o,s 5 10,11 and s,d and d with s 0110 ssss ssdd dddd z,s 5 10,11 test s,d bit test d with s 0111 ssss ssdd dddd z,s 5 10,11 or s,d or d with s 1000 ssss ssdd dddd z,s 5 10,11 xor s,d xor d with s 1001 ssss ssdd dddd z,s 5 10,11 jcc c,v jump relative on condition ? c ? 1100 cccc 0ooo oooo none 3 11 jccl c,d jump absolute on condition ? c ? 1100 cccc 10dd dddd none 4 11 rcc c return on condition ? c ? 1100 cccc 1001 0111 none 7 11 ccc c,d call subroutine on condition ? c ? 1010 cccc 10dd dddd none 7 11 int v software interrupt 1010 0000 0vvv vvvv none 7 11 shr n,d shift right out of carry 1101 000n nndd dddd z,c,s 4 10,12,11 shl n,d shift left into carry 1101 001n nndd dddd z,c,s 4 10,12,11 ror n,d rotate right 1101 010n nndd dddd z,c,s 4 10,12,11 rol n,d rotate left 1101 011n nndd dddd z,c,s 4 10,12,11 addi n,d add immediate 1101 100n nndd dddd z,s 4 11 subi n,d subtract immediate 1101 101n nndd dddd z,s 4 11 not d 1 ? s complement 1101 1110 00dd dddd z,s 4 11 neg d 2 ? s complement 1101 1110 01dd dddd z,o,c,s 4 11 cbw d sign-extend d(7:0) to d(15:0) 1101 1110 10dd dddd z,s 4 11 sti enable interrupts 1101 1111 1100 0000 none 3 11 cli disable interrupts 1101 1111 1100 0001 none 3 11 stc set carry 1101 1111 1100 0010 c 3 11 clc clear carry 1101 1111 1100 0011 c 3 11
SL11R document #: 38-08006 rev. ** page 67 of 85 b/w: ? 1 ? = byte access, ? 0 ? = word access. indirect with auto-increment and byte-wide indirect addressing is illegal with r15. 8.0 SL11R - electrical specification 8.1 absolute maximum ratings this section lists the absolute maximum ratings of the SL11R. stresses above those listed can cause permanent damage to the device. exposure to maximum rated conditions for extended periods can affect device operation and reliability. 8.2 recommended operating conditions opcode field descriptions clock adder field description addressing mode 5 4 3 2 1 0 s source register 0 0 r r r r 0 d destination immediate 0 1 1 1 1 1 0 c condition code direct 1 0 b/w 1 1 1 1 o signed offset indirect 0 1 b/w r r r 1 v interrupt vector indirect with auto increment 1 0 b/w r r r 2 n count value -1 indirect with index 1 1 b/w r r r 3 parameter range storage temperature ? 40 c to 125 c voltage on any pin with respect to ground ? 0.3v to 7.3v power supply voltage (vdd) 3.3v10% power supply voltage (vdd1) 3.3v10% lead temperature (10 seconds) 180 c junction temperature (tjmax) 125 c parameter min. typical max. power supply voltage, vdd 3.0v 3.3v 3.6v power supply voltage, vdd1 3.0v 3.6v operating temperature 0 c65 c
SL11R document #: 38-08006 rev. ** page 68 of 85 8.3 crystal requirements (xtal1, xtal2) 8.4 external clock input characteristics (xtal1) 8.5 SL11R dc characteristics crystal requirements, (xtal1, xtal2) min. typical max. operating temperature range 0 c65 c series resonant frequency 48 mhz frequency drift over temperature 20 ppm accuracy of adjustment 30 ppm series resistance 100 ? shunt capacitance 3 pf 6 pf load capacitance 20 pf driver level 20 w5 mw mode of vibration 3 rd overtone parameter min. typical max. clock input voltage @ xtal1 (xtal2 is opened) 1.5v clock frequency 48 mhz parameter description min. typical max. v il input voltage low ? 0.5v 0.8v v ih input voltage high 2.0v v dd + 0.3v v ol output voltage low (i ol = 4 ma) 0.4v v oh output voltage high (i oh = ? 4 ma) 2.4v i oh output current high 4 ma i ol output current low 4 ma c in input capacitance 20 pf i cc supply current (vdd) < 30 ma i usb supply current (vdd1) < 10 ma pd power dissipation 0.7w i cc +usb susp. suspend supply current < 220 a
SL11R document #: 38-08006 rev. ** page 69 of 85 8.6 SL11R usb transceiver characteristics notes: 13. all typical values are vddx = 3.3 v and tamb= 25 c. 14. z usbx impedance values includes an external resistor of 28-42 ? 1% 8.7 SL11R reset timing note : clock is 48 mhz nominal. 8.8 SL11R clock timing specifications parameter description min. typical [13] max. v ihys hysteresis on input (data+, data ? ) 0.1v 200 mv v usbih usb input voltage high 1.5 v 2.0v v usbil usb input voltage low 0.8v 1.3 v v usboh usb output voltage high 2.2v v usbol usb output voltage low 0.7v z usbh [14] output impedance high state 28 ? 42 ? z usbl [14] output impedance low state 28 ? 42 ? parameter description min. typical max. treset nreset pulse width 16 clocks tioact nreset high to nrd or nwrx active 16 clocks parameter description min. typical max. tclk clock period (48 mhz) 20.0 ns 20.8 ns thigh clock high time 9 ns 11 ns tlow clock low time 9 ns 11 ns trise clock rise time 5.0 ns tfall clock fall time 5.0 ns duty cycle ? 5% +5% nreset nrd or nwrl or nwrh treset tioact x1 trise tfall thigh tclk tlow
SL11R document #: 38-08006 rev. ** page 70 of 85 8.9 8/16-bit dma & dvc 8-bit dma mode: sdata port i/o read cycle (non-dma) note : rclk is the resulting clock (see register 0xc006) parameter description min. typical max. t apw addr pulse width 30 ns t cpw ncs pulse width 30 ns t rpw read pulse width 30 ns t acc read access time 25 ns t rdh read high to data hold 10 ns sd15-0 ncs nread rclk addr t rpw cpw t data valid t t rdh acc t apw
SL11R document #: 38-08006 rev. ** page 71 of 85 8.10 8/16-bit dma & dvc 8-bit dma mode: sdata port i/o write cycle (non-dma) note : rclk is the resulting clock (see register 0xc006) parameter description min. typical max. t apw addr pulse width 20 ns t cws ncs low to write high set-up 10 ns t wch write high to cs high hold 5 ns t wrpw write pulse width 10 ns t dws data setup to write high set-up 10 ns t wdh write high to data hold 5 ns sd15-0 ncs nwrite addr rclk t wrpw t apw cws wch t t dws data valid t t wdh
SL11R document #: 38-08006 rev. ** page 72 of 85 8.11 8/16-bit dma & dvc 8-bit dma mode: sdata, dma read cycle 8.12 8/16-bit dma & dvc 8-bit dma mode: sdata, dma write cycle 8.13 SL11R signals name convention doc. signal name SL11R pin name doc. signal name SL11R pin name /ras nras /we (dram) ndramwr /ucas ncash /lcas ncasl dout data15-0 /oe ndramoe din data15-0 address a20-0 /cs nxramsel /rd nrd /we (sram) nwrl & nwrh parameter description min. typical max. dcs dreq high to cs low 5 ns dr dreq high to read low 5 ns rdh read high to dreq low hold 30 ns parameter description min. typical max. dcs dreq high to cs low 5 ns dwdh write high to dreq low hold 30 ns dw dreq high to write low 5 ns rdh data valid d15-0 nread ncs dreq dr dcs wdh data valid d15-0 nwrite ncs dreq dw dcs
SL11R document #: 38-08006 rev. ** page 73 of 85 8.14 SL11R dram timing this timing is based on the SL11R processor clock (pclk) = (2/3) of rclk = 32mhz (see the register 0xc006 for information about pclk). note : this timing is base on edo dram timing 16mx16 devices. when the SL11R processor is set up for a higher speed (i.e. 48mhz clock), then the faster parts (i.e. 50ns or 60ns) should be used. parameter description min. typical max. t ras /ras pulse width 80 ns t cas /cas pulse width 20 ns t rp /ras precharge time 60 ns t rcd /ras to /cas delay time 64 ns t asr row address set-up time 20 ns t rah row address hold time 36 ns t asc column address set-up time 20 ns t cah column address hold time 36 ns t wcs write command set-up time 25 ns t ds data set-up time 05 ns t dh data hold time 40 ns t crp delay time, /cas pre-charge to /ras 05 ns t t transition time (rise and fall) 03 ns t rpc /ras precharge to /cas hold time 00 ns t csr /cas set-up time 05 ns t cpn /cas precharge time 10 ns t chr /cas hold time 60 ns t cac access time from /cas 20 ns t rac access time from /ras 80 ns t oac access time from /oe 20 ns t rc cycle time read 150 ns t off data out to high z 05 ns
SL11R document #: 38-08006 rev. ** page 74 of 85 8.15 SL11R dram read cycle row column ra s ucas lcas address we dout dout oe t rc t ras t rp t cas t rcd t asr t rah t rad t cah t asc t cac t oac t oep t rac
SL11R document #: 38-08006 rev. ** page 75 of 85 8.16 SL11R dram write cycle row column ra s ucas lcas address we din t rc t ras t rp t cas t rcd t asr t rah t cah t asc t rsh t csh t crp t wch t ds t dh t wcs
SL11R document #: 38-08006 rev. ** page 76 of 85 8.17 SL11R cas-before-ras refresh cycle a11-0 data15-0 high-z t off nras t rc ncasl ncash t rp t rc t rpc t ras t chr t ras t rp t rpc t csr t rp t csr t chr t crp t t t cpn t cpn
SL11R document #: 38-08006 rev. ** page 77 of 85 8.18 SL11R dram page mode read cycle t cdd t crp high-z column oe ras t rdd d out t cdd t wdd t odd t off2 t rch t oh t ohr t t rchr t t cal t rcha t t t t t t oac t rac t dzc t dzo t oep t t t t rah t rad t asr t csh t cas t t rcd t rp t ras t rc ucas lcas we d out d in
SL11R document #: 38-08006 rev. ** page 78 of 85 8.19 dram page mode write cycle high-z d out d in we address ucas lcas ras t rah t rah t wch t wcs column row t rah t rah t asc t cah t csh t rcd t cas t rsh t rp t t rc t ras
SL11R document #: 38-08006 rev. ** page 79 of 85 8.20 SL11R sram read cycle notes: 15. 0 wait state cycle. 16. t ac means at 0 wait states, with pclk = 2/3 rclk, the sram access time should be 12ns max. for a 1 wait state cycle, with pclk = 2 /3 rclk, the sram access time should be at 12 + 31ns = 43ns max. see register 0xc006 description for pclk information. parameter description min. typical max. t cr cs low to rd low 1 ns t rdh rd high to data hold 5 ns t cdh cs high to data hold 3 ns t rpw [15] rd low time 28 ns 31 ns t ar rd low to address valid 1 ns 3 ns t ac [16] ram access to data valid 12 ns address cs rd din t ar t rpw data valid t cr t ac t rdh t cdh
SL11R document #: 38-08006 rev. ** page 80 of 85 8.21 SL11R sram write cycle note: 17. this is at 1 wait state with pclk = 2/3 rclk. for 2-wait states, add 31 ns. parameter description min. typical max. t aw write address valid to we low 13 ns t csw cs low to we low 13 ns t dw data valid to we high 25 ns t wpw [17] we pulse width 28 ns t dh data hold from we high 5 ns t wc we high to cs high 15 ns address cs we dout t aw t csw t wpw t dw t wc t dh data valid
SL11R document #: 38-08006 rev. ** page 81 of 85 8.22 2-wire serial interface eeprom timing note : timing will conform to standard as illustrated in atmel at24cox data sheet parameter min./max. timing notes t low 4.7 s min. see atmel data sheet for t high 4.0 s min. complete timing detail t r 1.0 s max. t su1 200 ns max. t hold1 0 ns t su2 4.5 s min. t hold2 100 ns max. 1- eeprom bus timing- serial i/o 2- start and stop definition 3- data validity eeclk t low t high t r t su1 t hold1 t su2 t hold2 eedata in eedata out eedata eeclk start stop eeclk eedata data stable data change
SL11R document #: 38-08006 rev. ** page 82 of 85 8.23 fast epp data/address read cycle 8.24 fast epp data/address write cycle parameter description min. typical max. rpw ndtsrb or nastrb pulse width 50 ns rds data setup before ndtsrb or nastrb high 5 ns rdh ndtsrb or nastrb high to data hold 30 ns parameter description min. typical max. wpw nwrite pulse width 85 ns rpw ndtsrb or nastrb pulse width 50 ns wda nwrite low to ndtsrb or nastrb low 10 ns daw ndtsrb or nastrb high to nwrite high 25 ns wdh ndtsrb or nastrb high to data hold 30 ns data valid sd7-0 ndtsrb nastrb rpw ndtsrb nastrb nwrite
SL11R document #: 38-08006 rev. ** page 83 of 85 9.0 package information 9.1 drawings and dimensions
SL11R document #: 38-08006 rev. ** page 84 of 85 ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. 9.2 package markings yyww = date code xxxx = product code 9.3 thermal specifications parameter min. typ. max. junction temperature (t jmax ) 125 c package thermal impedance ( ja ) 65 c/w 75 c/w dissipated power @ 65 c ambient (p max ) 0.8w SL11R-ide yywwsqfp-1.2 xxxx
SL11R document #: 38-08006 rev. ** page 85 of 85 10.0 revision history document title: SL11R usb controller/16-bit risc processor data sheet document number: 38-08006 rev. ecn no. issue date orig. of change description of change ** 110565 12/14/01 bha converted to cypress format from scanlogic

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